多数据流并行卷积运算加速引擎研究与设计  

Research and design of multi-stream parallel convolution operation acceleration engine

作　　者：马佳利 朱智强[1] 戴乐育 郭松辉[1] 向建安 MA Jia-li;ZHU Zhi-qiang;DAI Le-yu;GUO Song-hui;XIANG Jian-an(Cipher Engineering Institute,Information Engineering University,Zhengzhou 450001,China;95010 PLA Troops,Shantou 515000,China)

机构地区：[1]信息工程大学密码工程学院,河南郑州450001 [2]95010部队,广东汕头515000

出　　处：《计算机工程与设计》2020年第12期3557-3562,共6页Computer Engineering and Design

基　　金：国家重点研发计划基金项目(2016YFB0501900)。

摘　　要：为解决卷积神经网络中卷积运算耗时长、运算复杂的问题,分析卷积运算的数据路由方式,提出一种多数据流并行卷积运算方法,实现卷积运算加速引擎的设计。通过在FPGA上进行实验验证,该设计能正确输出卷积运算的结果,相比已有加速器设计,所需寄存器数量减少30.6%,节省了逻辑资源,缩短了数据传输带来的时延,运算速度提升了7.37%,能够有效加速卷积运算完成。To solve the problem that the convolution operation in convolutional neural network is time-consuming and complica-ted,the data routing method of convolution operation was analyzed.A multi-stream parallel convolution operation method was proposed,and the convolution operation acceleration engine design was realized.By experimental verification on the FPGA,the design can correctly output the result of the convolution operation.Compared with the existing accelerator design,the required number of registers is reduced by 30.6%,which saves logic resources and shortens the delay caused by data transmission.The operation speed is increased by 7.37%,which can effectively accelerate the completion of the convolution operation.

关 键 词：卷积神经网络 卷积运算 现场可编程门阵列 并行处理 数据路由 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]