电流模控制高效同步DC-DC芯片设计  

Design of high⁃efficiency synchronous DC⁃DC chip controlled by current mode

作　　者：陈文琦 张涛[1] 刘劲[1] CHEN Wenqi;ZHANG Tao;LIU Jing(College of Information Science and Engineering,Wuhan University of Science and Technology,Wuhan 430080,China)

机构地区：[1]武汉科技大学信息科学与工程学院,湖北武汉430080

出　　处：《现代电子技术》2021年第2期13-16,共4页Modern Electronics Technique

基　　金：国家自然科学基金面上项目(61873196)。

摘　　要：采用0.18μm工艺设计一款同步高效降压型DC-DC电源芯片。为了实现快速响应、提高转换效率以及减小芯片面积的目的,该芯片采用电流模控制,应用电压外环与电流内环双环控制方式实现电路的快速响应和系统环路的稳定性。带补偿的电流检测电路能有效提高采样速度与精度。采用死区缓冲技术设计死区时间可调的缓冲器,并对误差放大器中补偿网络的电容采用电容倍增技术。仿真和测试结果表明,该芯片最高转换效率可达95%,平均转换效率为91.5%,输出纹波仅为0.3 mV,芯片面积约为1.2 mm~2,可广泛用于各类便携式电子产品中。A high⁃efficiency synchronous step⁃down DC⁃DC power supply chip is designed with 0.18μm process.In order to achieve fast response,improve conversion efficiency and reduce chip area,the current mode control is applied into the chip,and the double⁃loop control way which consists of outer voltage loop and inner current loop is used to achieve fast response of the circuit and stability of the system loop.The current detection circuit with compensation can effectively improve the sampling rate and accuracy.The dead⁃time buffering technology is used to design the buffer that the dead time is adjustable.The capacitance multiplication technology is used for the capacitance of the compensation network in the error amplifier.The simulation and testing results show that the chip′s maximum conversion efficiency can reach 95%,the average conversion efficiency is 91.5%,the output ripple is only 0.3 mV,and the chip area is about 1.2 mm2,which can be widely used in various portable electronic products.

关 键 词：DC-DC电源芯片 电流模控制 电路设计 死区缓冲 电容倍增技术 仿真测试 

分 类 号：TN366-34[电子电信—物理电子学]