基于FPGA的2D-Torus片上网络无死锁路由算法  

Deadlock-Free Routing Algorithm of 2D-Torus Network-on-Chip Based on FPGA

作　　者：李贞妮[1] 李晶皎[1] 王骄[1] 杨丹[1] LI Zhen-ni;LI Jing-jiao;WANG Jiao;YANG Dan(School of Information Science&Engineering,Northeastern University,Shenyang 110819,China)

机构地区：[1]东北大学信息科学与工程学院,辽宁沈阳110819

出　　处：《东北大学学报（自然科学版）》2021年第1期1-6,共6页Journal of Northeastern University(Natural Science)

基　　金：国家自然科学基金资助项目(61836011);中央高校基本科研业务费专项资金资助项目(2020GFYD011,2020GFZD008).

摘　　要：片上网络的拓扑结构和路由算法直接影响片上网络的传输延迟和传输效率.基于2D-Torus拓扑结构,提出了一种新的片上网络无死锁路由算法.通过改变数据包在片上网络路由过程中受限制转弯的位置,保证片上网络的自适应路由条件,从而有效降低片上网络的延迟.在FPGA硬件平台上,设计并实现了基于该路由算法的2D-Torus片上网络,并对其进行测试.实验结果表明,基于该路由算法的片上网络,可以满足片上网络多方向数据通信及多路数据并行通信等性能要求.The topology and routing algorithm of network on chip(NoC)directly influence the transmission delay and the transmission efficiency of the network-on-chip.A new deadlock-free routing algorithm for NoC was proposed based on 2D-Torus topology.By changing the position of packets that are restricted to turn during NoC routing,the adaptive routing condition of network-on-chip was guaranteed,and the delay of network-on-chip was reduced.The 2D-Torus NoC based on this routing algorithm was designed and implemented on FPGA hardware platform,and then was tested.The experimental results indicated that the NoC based on this routing algorithm can meet the performance requirements of network-on-chip data communication for multi-direction and multi-channel.

关 键 词：2D-TORUS 片上网络 无死锁 路由算法 FPGA 

分 类 号：TP393.0[自动化与计算机技术—计算机应用技术]