CAN FD控制器中可变速率的实现  

Realization of variable rate in CAN FD controller

作　　者：龙雅文 谢亮 金湘亮 LONG Ya-wen;XIE Liang;JIN Xiang-liang(School of Physics and Optoelectronics,Xiangtan University;Microelectronics and System Integration Hunan Engineering Laboratory;School of Physics and Electronics,Hunan Normal University)

机构地区：[1]湘潭大学物理与光电工程学院 [2]微光电与系统集成湖南省工程实验室 [3]湖南师范大学物理与电子科学学院

出　　处：《中国集成电路》2021年第1期37-41,共5页China lntegrated Circuit

摘　　要：传统的CAN总线受环路延迟的影响,传输速率无法突破1Mbps。本文根据CAN FD协议标准与国际标准ISO11898,采用硬件描述语言verilog设计,实现了CAN FD控制器的可变速率功能。控制器采用状态机实现对数据帧的接收,采用改变组成bit位中最小时间单元tq的周期长度实现速率切换,并在数据帧的data域应用二次采样机制解决发送节点的数据采样问题。另外整个设计中采用门控时钟技术、资源共享以及行波计数器来降低了设计的功耗。Due to the influence of loop delay,the transmission rate of traditional CAN bus can not exceed 1Mbps.According to CAN FD standard protocol and international standard ISO11898,the variable rate function of CAN FD controller is realized by using Hardware Description Language Verilog.The CAN FD controller uses the state machine to receive the data frame,the period length of the minimum time unit tq in the bit is changed to realize the rate switching,and the second sampling point is used in the data domain of the data frame to solve the data sampling problem of the sending node.In addition,clock gating technology,resource sharing and traveling wave counter are used to reduce the power consumption.

关 键 词：CAN FD控制器 可变速率 VERILOG 低功耗设计 

分 类 号：TP336[自动化与计算机技术—计算机系统结构]