基于FPGA的时序优化中值滤波算法研究  

Study on Timing Sequence Optimization Median Filter Algorithm Based on FPGA

作　　者：王正家[1,2] 吕召锐 刘文超 钱峰[1,2] WANG Zhengjia;LüZhaorui;LIU Wenchao;QIAN Feng(School of Mechanical Engineering,Hubei University of Technology,Wuhani Hubei 430068,China;Hubei Key Lab of Manufacture Quality Engineering,Wuhan Hubei 430068,China)

机构地区：[1]湖北工业大学机械工程学院,湖北武汉430068 [2]现代制造质量工程湖北省重点实验室,湖北武汉430068

出　　处：《电子器件》2020年第6期1374-1378,共5页Chinese Journal of Electron Devices

基　　金：国家自然科学基金项目(51575164)。

摘　　要：针对现场可编程门阵列(FPGA)实现图像中值滤波处理时,面临着提高FPGA运行时钟频率和优化硬件资源相冲突的问题,提出一种时序优化中值滤波算法。该算法先通过二输入比较器级联模块代替三输入比较器模块,实现数据多拍处理,减少算法的硬件时序迟滞,提高算法在FPGA上的运行时钟频率。接着使用极值比较器模块对算法的并行运算流程进行优化,节省硬件资源,缩短算法耗时。仿真结果表明:对3*3滤波器,算法8个时钟周期后输出首个中值,后续每个时钟周期输出1个中值,理论稳定运行的最高时钟频率为231.2 MHz。When using Field Programmable Gate Array(FPGA)to realize image median filtering processing,it was faced with the conflict between increasing FPGA working clock frequency and optimizing hardware resources,a time optimization median filter algorithm was proposed,this algorithm first replaced the three input comparator with the two input comparator cascade module to realize multi-beat processing of data,reduced the algorithm’s hardware timing delay,and improved the working clock frequency of FPGA.Then,the extremum comparator module was used to optimize the parallel operation process of the algorithm to save hardware resources and shorten the clock cycle of the algorithm.Simulation results showed that:for the 3*3 filter,the algorithm outputted the first median after 8 clock cycles,and then outputted 1 median for each subsequent clock cycle.The maximum clock frequency of theoretical stable operation was 231.2 MHz.

关 键 词：现场可编程门阵列 中值滤波 时序优化 比较器 多拍处理 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]