一种基于位交错结构的亚阈值10管SRAM单元  

A Subthreshold 10T SRAM Cell Based on Bit-Interleaving Architecture

作　　者：吴晓清 吕嘉洵 黄茂航 贺雅娟[1] WU Xiaoqing;Lü Jiaxun;HUANG Maohang;HE Yajuan(State Key Lab.of Elec.Thin Films and Inter.Dev.,Univ.of Elec.Sci.and Technol.of China,Chengdu 610054,P.R.China)

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,成都610054

出　　处：《微电子学》2020年第6期839-843,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61874023);中央高校基本科研业务费基金资助项目(ZYGX2018J030);预研基金资助项目(31513030209)。

摘　　要：提出了一种基于位交错结构的亚阈值10管SRAM单元,实现了电路在超低电压下能稳定地工作,并降低了电路功耗。采用内在读辅助技术消除了读干扰问题,有效提高了低压下的读稳定性。采用削弱单元反馈环路的写辅助技术,极大提高了写能力。该10管SRAM单元可消除半选干扰问题,提高位交错结构的抗软错误能力。在40 nm CMOS工艺下对电路进行了仿真。结果表明,该10管SRAM单元在低压下具有较高的读稳定性和优异的写能力。在0.4 V工作电压下,该10管SRAM单元的写裕度为传统6管单元的14.55倍。A subthreshold 10 T SRAM cell based on bit-interleaving architecture was proposed, which could work stably under ultra-low voltage and reduce circuit power consumption. The built-in read assist scheme eliminated the read disturb issue and effectively improved the read stability under low voltage. The write ability was greatly improved by using the write assist technique which weakened the feedback loop of the cell. The 10 T SRAM cell could eliminate the half-select disturb and improve the soft error immunity of the bit-interleaving architecture. The circuit was simulated in a 40 nm standard CMOS process. The results indicated that the 10 T SRAM cell had high read stability and excellent write ability under low voltage. At 0.4 V supply voltage, the write margin of the 10 T SRAM cell was 14.55 times larger than that of the conventional 6 T cell.

关 键 词：超低压SRAM 低功耗 稳定性 软错误 

分 类 号：TN432[电子电信—微电子学与固体电子学]