基于FPGA/CPLD级联多电平PWM信号快速关断控制策略  

Fast Turning-off Scheme of PWM Signals for Cascaded Multilevel Converters Based on FPGA/CPLD

作　　者：陈兮 黄声华[2] 张先鹤 CHEN Xi;HUANG Shenghua;ZHANG Xianhe(School of Mechatronics and Control Engineering, Hubei Normal University, Huangshi Hubei 435002, China;School of Electrical and Electronic Engineering, Huazhong University of Science & Technology,Wuhan 430074, China)

机构地区：[1]湖北师范大学机电与控制工程学院,湖北黄石435002 [2]华中科技大学电气与电子工程学院,武汉430074

出　　处：《微电机》2021年第1期39-44,共6页Micromotors

基　　金：国家自然科学基金资助项目(61370093);湖北省教育厅科学研究计划指导性项目(B2020132)。

摘　　要：本文针对多电平变换器使能信号延迟造成PWM信号无法快速关断问题进行分析,提出一种特定形式PWM信号编解码方法。文中首先概述级联多电平电路特点与调制策略;然后,详细讨论和分析了基于DSP/FPGA/CPLD/MCU级联五电平变换器控制系统使能信号延迟的本质原因,设计出一种既能传输PWM驱动信号又能快速传输使能信号的方法,该方法可以极大减小使能信号时间延迟,实现多电平变换器PWM信号快速关断,同时兼有滤除极窄驱动脉冲特性。最后,实验结果验证了本文方法的有效性。The problem that pulse width modulation(PWM)signal cannot be turned off fast due to the delay of enable instruction was analyzed in multilevel converters,and a novel encoding and decoding method of PWM signal was proposed in this paper.Firstly,a brief introduction of cascaded multilevel converters was given and the modulation strategy was presented.Secondly,the essence of enable instruction delay in cascaded five-level converter based on digital signal processor(DSP),field programmable gate array(FPGA),complex programmable logic device(CPLD)and microcontroller unit(MCU)was discussed and analyzed in detail,and a method that can transmit not only PWM signals but also enable instruction fast was designed.With the proposed scheme,the time delay of enable instruction was greatly reduced and PWM signals were turned off fast in multilevel converters,and the narrow pulses were also filtered out.Finally,experimental results verified the validity of the proposed scheme.

关 键 词：FPGA/CPLD PWM 级联多电平 快速关断 

分 类 号：TM464[电气工程—电器] TP273[自动化与计算机技术—检测技术与自动化装置]