码率兼容空间耦合LDPC码编码器与译码器设计  

Design of rate-compatible spatially coupled LDPC code encoder and decoder

作　　者：张恒皞 丛惠平 赵旦峰[1] ZHANG Henghao;CONG Huiping;ZHAO Danfeng(College of Information and Communication Engineering,Harbin Engineering University,Harbin 150001,China;Unit 91033,PLA,Qingdao 266071,China)

机构地区：[1]哈尔滨工程大学信息与通信工程学院,黑龙江哈尔滨150001 [2]中国人民解放军91033部队,山东青岛266071

出　　处：《应用科技》2020年第6期23-29,共7页Applied Science and Technology

摘　　要：为了实现不同信道条件下的信道编码硬件实现方案,本文构造了一种码率兼容的空间耦合低密度奇偶校验(SCLDPC)码,并进行了编码器与译码器的现场可编程门阵列(FPGA)实现。编码器采用部分校验子前项编码算法进行不同码率的快速递归编码。译码器采用最小和算法,结合分层译码结构完成译码。该设计在Xilinx xc7k325tffg900-2芯片上进行测试,实现了3种不同码率的空间耦合LDPC码的编码与译码功能,具有良好的译码性能和较低的资源占用率。In order to realize the hardware implementation of channel coding under different channel conditions,a ratecompatible spatially coupled low density parity check code(SC-LDPC)is constructed,and the encoder and decoder are implemented in field programmable gate array(FPGA).The encoder uses partial syndrome antecedent coding algorithm to perform fast recursive coding of different code rates.The decoder uses the minimum sum algorithm,combined with a layered decoding structure to complete the decoding.The design was tested on the Xilinx xc7k325tffg900-2 chip,and realized the encoding and decoding functions of three spatially coupled LDPC codes with different code rates,with good decoding performance and low resource occupation.

关 键 词：空间耦合LDPC 码率兼容 编码器 部分校验子前项 译码器 最小和算法 分层译码算法 现场可编程门阵列 

分 类 号：TN911.22[电子电信—通信与信息系统]