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作 者:李雨倩 焦继业 刘有耀 郝振和 LI Yuqian;JIAO Jiye;LIU Youyao;HAO Zhenhe(School of Electronic Engineering,Xi’an University of Posts&Telecommunications,Xi’an 710121,China;School of Computer Science and Technology,Xi’an University of Posts&Telecommunications,Xi’an 710121,China)
机构地区:[1]西安邮电大学电子工程学院,西安710121 [2]西安邮电大学计算机学院,西安710121
出 处:《计算机工程》2021年第2期261-267,284,共8页Computer Engineering
基 金:国家自然科学基金(61874087)。
摘 要:为满足嵌入式设备小面积高性能的需求,设计一种基于开源RISC-V指令集的32位可综合乱序处理器。处理器包括分支预测、相关性处理等关键技术,支持RISC-V基本整数运算、乘除法以及压缩指令集。采用具有顺序单发射、乱序执行、乱序写回等特性的三级流水线结构,运用哈佛体系结构及AHB总线协议,可满足并行访问指令与数据的需求。在Artix-7(XC7A35T-L1CSG324I)FPGA开发板上以50MHz时钟频率完成功能验证,测试功耗为7.9mW。实验结果表明,在SMIC110nm的ASIC技术节点上进行综合分析,并在同等条件下与ARM CortexM3等处理器进行对比,该系统面积减少64%,功耗降低0.57mW,可用于小面积低功耗的嵌入式领域。In order to meet the high performance and small area requirements of embedded devices,this paper designs and implements a32-bit integrated out-of-order processor based on open source RISC-V instruction set.The processor includes the design of key technologies such as branch prediction and correlation processing,supporting basic integer operations,multiplication,division and compressed instruction set of RISC-V.It adopts a3-stage assembly line structure that is characterized by sequential single transmission,out-of-order execution,out-of-order write-back,etc.By taking the AHB bus protocol for on-chip bus and using Harvard architecture,the demands of parallel access to instructions and data can be met. The functional verification is completed on the ARTIX-7(XC7 A35 T-L1 CSG324 i)FPGA development board with a clock frequency of50 MHz,and the test power consumption is7.9 mW. The experimental results is comprehensively analyzed on the SMIC110 nm ASIC technology node,and compared with ARM Cortex-M3 processors under the same conditions. Results show that the system area is reduced by64% and power consumption reduced by0.57 mW,which demonstrates that it can be used in embedded devices that require small area and low power consumption.
关 键 词:RISC-V指令集 嵌入式应用 乱序处理器 微体系结构 三级流水线
分 类 号:TP332[自动化与计算机技术—计算机系统结构]
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