CMOS密勒补偿三级放大器建立时间的最优设计  

Optimal settling time design for CMOS three-stage miller compensated amplifiers

作　　者：蒋新淼 郭裕顺[1] JIANG Xinmiao;GUO Yushun(School of Electronic Information,Hangzhou Dianzi University,Hangzhou Zhejiang 310018,China)

机构地区：[1]杭州电子科技大学电子信息学院,浙江杭州310018

出　　处：《杭州电子科技大学学报（自然科学版）》2021年第2期21-26,共6页Journal of Hangzhou Dianzi University：Natural Sciences

摘　　要：提出一种CMOS密勒补偿三级运放建立时间的最优设计方法。在给定的建立时间精度要求下,从基于传递函数得到的近似设计结果出发,根据响应建立时间最小应满足的方程,通过Newton迭代自动求解最佳设计参数。由于求解过程中的时域响应直接使用了电路SPICE仿真波形,因此可消除现有方法中存在的误差,得到准确的设计结果,避免了电路级设计所需的人工调试。以嵌套式密勒补偿三级运算放大器为例,给出0.35μm和90 nm下的设计结果,验证了设计方法的有效性。An optimal design method for settling time of CMOS three-stage Miller compensated amplifiers is proposed.Under the given settling time accuracy.This method attempts to find the exact solution from the formulated equations based on the settling time minimization condition by the Newton iteration,where the initial solution is given by the previous approximate transfer function based method.Since the SPICE simulated response waveform is used in the entire solution process,the errors existed in the previous methods are eliminated,more accurate design results are obtained,and the tedious manual tuning in the circuit design phase is avoided.An example of the nested Miller compensated three-stage operational amplifier design is provided.The design results under 0.35μm and 90 nm technology demonstrate the effectiveness of this method.

关 键 词：多级运算放大器 建立时间 密勒补偿 

分 类 号：TN402[电子电信—微电子学与固体电子学]