强电场下亚微米ESD注入型NMOS IDT-VGS微分负阻现象研究  

Study on Differential Negative Resistance of Submicron ESD-Implanted NMOS I_(DT)-V_(GS) Under High Electric Field

作　　者：刘玉奎[1] 殷万军 谭开洲[1,2] 崔伟[1,2] LIU Yukui;YIN Wanjun;TAN Kaizhou;CUI Wei(The 24th Research Institute of China Electronics Technology Group Corporation,Chongqing 400060,P.R.China;Science and Technology on Analog Integrated Circuit Laboratory,Chongqing 400060,P.R.China)

机构地区：[1]中国电子科技集团公司第二十四研究所,重庆400060 [2]模拟集成电路国家重点实验室,重庆400060

出　　处：《微电子学》2021年第1期112-115,120,共5页Microelectronics

基　　金：重庆市科委基金资助项目(scc2019jscx-fxyd0178)。

摘　　要：采用优化ESD注入条件改善了NMOS器件结构。对该亚微米ggNMOS ESD防护电路单元进行了传输线脉冲TLP法测试。测试结果表明,优化后的多插指通道保护结构的静电释放电流均匀性得到改善。对该ESD注入型NMOS输出特性的研究发现,在强场下漏极电流I_(DT)是一种复合电流,随着栅源电压超过阈值V_(GS)0,它会呈现I_(DT)-V_(GS)微分负阻现象。从MOS-Bipolar复合模式下的碰撞电离和Snapback效应两方面对I_(DT)-V_(GS)微分负阻现象进行了理论分析。研究结果可用于优化CMOS/BiCMOS IC的ESD设计。The structure of NMOS device was improved by optimizing ESD implanted process parameters.The submicron ggNMOS ESD protection circuit unit was tested by transmission line pulse TLP method. The test results showed that the uniformity of electrostatic discharge current was improved after the optimization. The study of the output characteristics of the ESD-implanted NMOS showed that the drain terminal current I_(DT) was a compound current, and it exhibited I_(DT)-V_(GS) differential negative resistance phenomenon under high electric field when gate-source voltage V_(GS) was more than the threshold value V_(GS)0. The theoretical analysis of I_(DT)-V_(GS) differential negative resistance phenomenon from impact ionization and snapback effect at MOS-Bipolar hybrid mode were presented. The research results of this paper could be used to optimize ESD design of CMOS/BiCMOS IC.

关 键 词：微分负阻 碰撞电离 MOS-Bipolar复合模式 静电释放 

分 类 号：TN386[电子电信—物理电子学]