一种多核处理器直连接口QoS的设计与验证  

QoS design and verification of direct connection interface for multi-core processors

作　　者：罗莉[1] 周宏伟[1] 周理[1] 潘国腾[1] 周海亮 刘彬 LUO Li;ZHOU Hong-wei;ZHOU Li;PAN Guo-teng;ZHOU Hai-liang;LIU Bin(College of Computer Science and Technology,National University of Defense Technology,Changsha 410073;Armed Police Corps,Guizhou Province,Guiyang 550081,China)

机构地区：[1]国防科技大学计算机学院,湖南长沙410073 [2]武警贵州省总队,贵州贵阳550081

出　　处：《计算机工程与科学》2021年第4期620-627,共8页Computer Engineering & Science

基　　金：国家重点研发计划(2018YFB0204301)。

摘　　要：多核处理器直接互连构建多路并行系统,一直是提高高性能计算机并行性的主要方式。主要研究多核处理器直连接口的QoS设计,通过直连接口完成跨芯片的Cache一致性报文有效、可靠传输,实现共享主存的SMP系统。详细阐述了直连接口各个协议层的QoS设计的关键技术,基于UVM方法学构建了可重用验证平台,模拟验证了QoS设计的正确性,移植到FPGA原型验证平台,顺利通过了测试。深入研究和实现处理器芯片直连技术,是提升高性能多路服务器的主流方向,具有良好的应用和研究前景。Direct connection of multi-core processors to build multi-way parallel systems has always been the main way to improve the parallelism of high-performance computers.This paper mainly studies the QoS design and verification of the multi-core processor’s direct connection interface.Through the direct connection interface,the cache consistent message across the chip can be effectively and reliably transmitted,and the SMP system(symmetric multiprocessing)sharing main memory can be realized.In this paper,the key technologies of QoS design for each protocol layer of direct connection interface are described in detail.After the validity of QoS design is verified by the reusable verification platform based on UVM method,it has been transplanted to the FPGA prototype verification platform and passed the test successfully.In order to improve the performance of multi-way servers,it is necessary to further study the direct connection technology of multi-core processors,which has good application and research prospects.

关 键 词：多核处理器直连接口 SMP系统 QoS设计 UVM验证 

分 类 号：TP302.1[自动化与计算机技术—计算机系统结构]