一种应用于软件定义互连系统的多协议SerDes电路  

A Multi-Protocol SerDes Circuit for the Applications in Software Defined Interconnection System

作　　者：李沛杰 沈剑良 苑红晓 王永胜 夏云飞 张传波 LI Pei-jie;SHEN Jian-liang;YUAN Hong-xiao;WANG Yong-sheng;XIA Yun-fei;ZHANG Chuan-bo(Information Engineering University,Zhengzhou,Henan 450002,China;Troop 32125,Jinan,Shandong 250100,China;Information Technology Innovation Center of Tianjin Binhai New Area,Tianjin 300457,China)

机构地区：[1]中国人民解放军战略支援部队信息工程大学,河南郑州450002 [2]32125部队,山东济南250100 [3]天津市滨海新区信息技术创新中心,天津300457

出　　处：《电子学报》2021年第4期817-823,共7页Acta Electronica Sinica

基　　金：国家科技重大专项核高基项目(No.2016ZX01012101)。

摘　　要：为满足片上系统的柔性互连,提出一种应用于软件定义互连系统的1.0625~10.3125Gbps多协议SerDes电路结构.该电路采用统一架构实现不同协议的规范需求,通过一种1×QPLL+4×Lane PLL的时钟结构实现宽频点和低抖动的时钟输出,通过可编程的发送端前向反馈均衡器和接收端线性均衡器和判决反馈均衡器电路,实现最大32dB的插损补偿.测试结果表明,所设计的SerDes电路在10.3125Gbps速率下发送总抖动为21.2ps,随机抖动均方根值为633.7fs,最大功耗29.33mW/Gbps,发送端眼图和接收端抖动容限及误码率均能够满足FC-PI-4,RapidIO 3.0,10GBase-KR,1000Base-X的协议规范要求.In order to meet the application requirements of flexible interconnection in system on chip(SoC),a 1.0625~10.3125Gbps multi-protocol SerDes circuit for software defined interconnection(SDI)system is proposed.The circuit uses a unified architecture to meet the requirements of different protocols.A 1×QPLL+4×Lane PLL structure is implemented to achieve the broadband data rate and the low jitter output.The 32dB channel loss compensation is achieved by programmable feed forward equalizer(FFE),continuous time linear equalizer(CTLE)and decision feedback equalizer(DFE)circuits.The output measures 21.2ps total jitter(TJ)and 633.7fs random jitter(RJ)RMS.The power efficiency of the test chip is 29.33mW/Gbps at 10.3125 Gbps.The output eye pattern of the transmitter,the jitter tolerance and the bit error rate of the receiver can meet the protocol specifications of FC-PI-4,RapidIO 3.0,10GBase-KR and 1000Base-X.

关 键 词：软件定义互连 SERDES 时钟数据恢复 锁相环 高速串行收发器 数模混合电路 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]