USB音频设备中同步时钟系统的设计  

Design of Synchronous Clock System in USB Audio Device

作　　者：来鹏飞 李良 徐晟阳 邹林均 LAI Pengfei;LI Liang;XU Shengyang;ZOU Linjun(Wuxi 1-CORE Electronics Co.,Ltd.,Wuxi Jiangsu 214072,China)

机构地区：[1]无锡中微爱芯电子有限公司,江苏无锡214072

出　　处：《电子器件》2021年第2期306-311,共6页Chinese Journal of Electron Devices

摘　　要：USB通信协议采用2线差分(D+/D-)信号传输数据,主机与从机(USB设备)之间没有专门的同步时钟连线,数据传输的同步信息包含在数据包的同步字段。为了保证通信可靠正确的进行,从机的数据同步时钟频率必须严格跟随主机数据比特信息的时序。为此设计了一款应用于USB音频外设的电荷泵锁相环(CPPLL),输入参考时钟采用小数分频的方式,动态跟随主机传输速率的变化,最终PLL产生的系统时钟精度可达±0.05%,锁定时间小于70μs,频率跟随范围为70 MHz~230 MHz。该设计采用0.153μm CMOS工艺流片,实测结果表明所设计时钟系统能够提供精确相位和频率的时钟,确保音频设备与主机可靠正确的通信。The USB communication protocol adopts two-wire differential(D+/D-)signal to transmit data. There is no special synchronization clock connection between the host and the slave(USB device). The synchronization information of data transmission is contained in the synchronization field of the packet. In order to ensure reliable and correct communication, the slave data synchronization clock frequency must strictly follow the timing of the host data bits. Charge pump phase-locked loop(CPPLL)is designed for USB audio peripherals, in which the input reference clock follows the change of the host transmission rate by the method of fractional frequency division. The clock accuracy of PLL system is ±0.05%,the lock time is less than 70 μs, and the follow range is 70 MHz to 230 MHz. The 0.153 μm CMOS process flow sheet is adopted in this design. The measured results show that the designed PLL can provide precise phase and frequency of the system clock, to ensure correct audio equipment with the host and reliable communication.

关 键 词：通用串行总线通信 电荷泵锁相环 小数分频 

分 类 号：TN751[电子电信—电路与系统]