用于卫星载荷数据传输总线的终端IP核设计  

Design of the RT IP Core for Satellite Payload Data Bus

作　　者：刘文婷[1] 万小磊[1] 徐楠[1] 杨童[1] 陈亮亮[1] LIU Wenting;WAN Xiaolei;XU Nan;YANG Tong;CHEN Liangliang(Institute of Telecommunication and Navigation Satellites,China Academy of Space Technology,Beijing 100094,China)

机构地区：[1]中国空间技术研究院通信与导航卫星总体部,北京100094

出　　处：《应用科学学报》2021年第2期232-240,共9页Journal of Applied Sciences

基　　金：国家科技重大专项(No.2017ZX01013101-003)资助。

摘　　要：根据通信卫星有效载荷数据传输总线协议及其工作原理,提出了一种总线终端IP(intellectual property)核的设计及验证方法,该IP核由总线接口模块、时钟分频模块、协议处理模块、数据采集模块等组成,其设计和研制具有自主知识产权。该IP核完成了模块仿真验证、芯片系统仿真验证和FPGA(field programmable gate array)验证并已流片成功,验证结果表明:该IP核设计功能全面、资源占用少、可靠性高,可应用于通信卫星地检验证设备或者直接应用于卫星有效载荷设备中,支持通信卫星有效载荷数据传输总线的测试。Based on serial bus protocol,a remote terminal IP(intellectual property)core for satellite payload data bus is proposed.The IP core is composed of bus interface module,frequency divider module,protocol processing module and data collecting module.The IP core design is tested and verified by functional simulation and FPGA(field programmable gate array)test,and has been taped out successfully.Test results indicate that the designed IP core has good performance in capability,reliability and less resource occupancy.It can be used for testing the payload data bus in satellite systems or in verification equipment of satellite systems.

关 键 词：通信卫星 载荷数据传输总线 IP核 总线终端 FPGA验证 

分 类 号：V443[航空宇航科学与技术—飞行器设计]