基于130nm SOI工艺数字ASIC ESD防护设计  

ESD Protection Design for Digital ASIC Based on 130nm SOI Technology

作　　者：米丹 周昕杰 周晓彬 Mi Dan;Zhou Xinjie;Zhou Xiaobin(The 58^(th)Research Institute,CETC,Wuxi 214072,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214072

出　　处：《半导体技术》2021年第4期279-285,共7页Semiconductor Technology

摘　　要：绝缘体上硅(SOI)工艺具有寄生电容小、速度快和抗闩锁等优点,成为低功耗和高性能集成电路(IC)的首选。但SOI工艺IC更易受自加热效应(SHE)的影响,因此静电放电(ESD)防护设计成为一大技术难点。设计了一款基于130 nm部分耗尽型SOI(PD-SOI)工艺的数字专用IC(ASIC)。针对SOI工艺ESD防护设计难点,进行了全芯片ESD防护原理分析,通过对ESD防护器件、I/O管脚ESD防护电路、电源钳位电路和ESD防护网络的优化设计,有效减小了SHE的影响。该电路通过了4.5 kV人体模型ESD测试,相比国内外同类电路有较大提高,可以为深亚微米SOI工艺IC ESD防护设计提供参考。The silicon on insulator(SOI)technology has advantages of small parasitic capacitance,fast speed and anti latch-up,so it has become a preference for the low power consumption and high performance integrated circuits(ICs).However,the IC based on SOI technology is more susceptible to self-heating effects(SHEs),so the design of electrostatic discharge(ESD)protection becomes a major technical difficulty.A digital application specific IC(ASIC)based on 130 nm partially depleted SOI(PD-SOI)technology was designed.In view of the ESD protection design difficulty on SOI technology,the principle of whole-chip ESD protection was analyzed.By optimizing the design of an ESD protection device,an I/O pin ESD protection circuit,a power clamp circuit and an ESD protection network,the SHE influence was effectively reduced.The circuit has passed a 4.5 k V human body model ESD test,and it is greatly improved compared with other similar circuits at home and abroad.It can provide a reference for the IC ESD protection design based on deep submicron SOI technology.

关 键 词：深亚微米 绝缘体上硅(SOI)工艺 全芯片 静电放电(ESD)防护 电源钳位 人体模型 

分 类 号：TN492[电子电信—微电子学与固体电子学]