基于FPGA的DDR2 SDRAM控制器设计  

Design of DDR2 SDRAM controller based on FPGA

作　　者：钱素琴[1] 刘晶华 Qian Suqin;Liu Jinghua(College of information science and technology,Donghua University,Shanghai,201600)

机构地区：[1]东华大学信息科学与技术学院,上海201600

出　　处：《电子测试》2021年第11期9-12,共4页Electronic Test

摘　　要：基于高速数据传输与存储的数据采集记录仪对缓存模块高性能的需求,选择了读写速度快、低成本、大容量、运行稳定的DDR2 SDRAM作为本地存储器,在其存储寻址原理和IP核的读写控制逻辑的基础上,借助硬件描述语言设计了一个DDR2存储控制器方案。在Intel的FPGA Cyclone IV系列开发板上进行了整体方案的功能验证,完成了用户接口和控制器之间的多数据宽度、多突发长度的高效数据传输和读写操作,在166.7MHz时钟频率下实现了稳定读写的目标。Based on the requirement of high-speed data transmission and storage data acquisition recorder for high performance of cache module,DDR2 SDRAM with high read-write speed,low cost,large capacity and stable operation is selected as the local memory.Based on its storage addressing principle and the read-write control logic of IP core,a DDR2 storage controller scheme is designed with the help of hardware description language.The functional verification of the overall scheme is carried out on the FPGA cyclone IV series development board of Intel.The efficient data transmission and read-write operation of multiple data widths and burst lengths between the user interface and the controller are completed.The stable read-write target is achieved at 166.7MHz clock frequency.

关 键 词：FPGA DDR2 SDRAM IP核 

分 类 号：TP332[自动化与计算机技术—计算机系统结构] N7[自动化与计算机技术—计算机科学与技术]