用于不同体态芯片互连的凸点制备及性能表征  

Fabrication and Characterization of Micro⁃bumps for Inter⁃connection of Different Body Chips

作　　者：陈聪 李杰 姜理利[1] 吴璟[1] 张岩 郁元卫[1,2] 黄旼 朱健[1,2] CHEN Cong;LI Jie;JIANG Lili;WU Jing;ZHANG Yan;YU Yuanwei;HUANG Min;ZHU Jian(Nanjing Electronic Devices Institute,Nanjing,210016,CHN;Science and Technology on Monolithic Integrated Circuits and Modules Laboratory,Nanjing,210016,CHN)

机构地区：[1]南京电子器件研究所,南京210016 [2]微波毫米波单片集成和模块电路重点实验室,南京210016

出　　处：《固体电子学研究与进展》2021年第2期87-92,共6页Research & Progress of SSE

摘　　要：随着轻量化、小型化及模块功能多样化的发展,由二维平面到三维高度上的先进封装技术应运而生。微凸点作为实现芯片到圆片异构集成的关键结构,可有效缩短信号传输距离,提升芯片性能。利用电沉积法在Si基板上以Cu作支撑层、Ni作阻挡层淀积微米级别的Au/Sn凸点,所制得的多层凸点直径约60μm、高度约54μm,其高度可控、尺寸可调,并研究了Die内凸点高度的一致性,同时对凸点进行了剪切强度和推拉力测试。结果表明,Die内凸点高度均匀性≤2%,剪切力可达61.72 g以上,与化合物芯片(另一侧为Au)键合后推拉力可达7.5 kgf,可实现与化合物芯片的有效集成。With the development of lightweight,miniaturization and module function diversifica⁃tion,advanced packaging technology from 2D plane to 3D height has emerged.As a key process for realizing 3D heterogeneous integration of chip to wafer,micro-bumps could effectively shorten the sig⁃nal transmission distance and improved chip performance.In this paper,Au/Sn bumps of micron scale were deposited on silicon wafers by electroplating with Cu as support layer and Ni as barrier layer.The diameter and height of the multi-layer bumps are about 60μm and 54μm,respectively.The height of the bumps is controllable and the size is adjustable.Furthermore,the consistency of the height of the bumps in a die was studied,and the shear strength and push-pull force were tested.The results show that the height uniformity of bumps in a die is≤2%,the shear strength is up to 61.72 g,and the push-pull force is up to 7.5 kgf after bonding with the compound chip,which can realize effec⁃tive integration with the compound chip.

关 键 词：3D封装 微凸点 电沉积 Au/Sn 

分 类 号：TN305.94[电子电信—物理电子学]