数字锁相环的相位噪声分析  

Analysis of Phase Noise in Digital Phase-locked Loop

作　　者：张占荣 王云飞 屈美霞 赵丽 ZHANG Zhanrong;WANG Yunfei;QU Meixia;ZHAO Li(Department of Mechanical and Electrical Engineering,Ordos Vocational College of Eco-environment,Ordos 017010,Nei Moggol,China;Basic Department,Ordos Vocational College of Eco-environment,Ordos 017010,Nei Moggol,China;School of Software,Shanxi University,Taiyuan 030013,Shanxi,China)

机构地区：[1]鄂尔多斯生态环境职业学院机电工程系,内蒙古鄂尔多斯017010 [2]鄂尔多斯生态环境职业学院基础部,内蒙古鄂尔多斯017010 [3]山西大学软件学院,山西太原030013

出　　处：《电气传动》2021年第11期15-19,共5页Electric Drive

基　　金：山西省科技厅基础研究计划项目—青年科技研究基金(2014021039-6)。

摘　　要：随着信息化社会的发展,数字锁相环越发受研发人员的重视。而相位噪声是衡量数字锁相环性能的关键技术,更是研究的重点。介绍数字锁相环的组成结构和工作原理,建立环路各个模块的相位噪声模型,从闪烁噪声和白噪声的特性入手,定性分析相位噪声的影响因素,并针对电荷泵增益和环路滤波器阻抗对锁相环电路相位噪声的影响进行了仿真,进一步验证了分析结果,为设计高性能的数字锁相环提供理论基础。With the development of information society,digital phase-locked loop(DPLL)attracts more and more attention of researchers.As the key technology to evaluate the performance of DPLL,phase noise becomes the key point of the study.The structure and work principle of DPLL were introduced,the phase noise model of each module of the loop was established.Starting from the characteristics of flicker noise and white noise,the influence factors of phase noise were analyzed qualitatively,and the influence of charge pump gain and loop filter impedance on phase noise of PLL circuit was simulated to further verify the analysis results.The theoretical basis was provided for improving the phase noise performance of DPLL.

关 键 词：数字锁相环 相位噪声 振荡器 电荷泵 环路滤波器 

分 类 号：TM28[一般工业技术—材料科学与工程]