一种高性能的亚阈值CMOS电压基准  

A High Performance Sub-Threshold CMOS Voltage Reference

作　　者：王远飞[1] 罗萍[1] 杨健[1] 唐天缘 杨秉中 WANG Yuanfei;LUO Ping;YANG Jian;TANG Tianyuan;YANG Bingzhong(School of Elec.Sci.and Engineer.,Univ.o f Elec.Sci.and Technol.of China,Chengdu 610053,P.R.China)

机构地区：[1]电子科技大学电子科学与工程学院,成都610053

出　　处：《微电子学》2021年第2期163-167,共5页Microelectronics

基　　金：预研基金资助项目(1126190601A)。

摘　　要：基于0.18μm CMOS工艺设计了一种高性能的亚阈值CMOS电压基准。提出了一个电压减法电路,将两个具有不同阈值电压且工作在亚阈值区晶体管的栅源电压差作为电压基准输出。所提出的电压减法电路还可以很好地消除电源电压变化对输出基准的影响。后仿仿真结果表明,所设计的电压基准在0.55~1.8 V电源电压范围内,线性灵敏度为0.053%/V~0.121%/V;在-20℃~80℃范围内,温度系数为9.5×10^(-6)/℃~3.49×10^(-5)/℃;在tt工艺角、0.55 V电源电压下,电源抑制比为-65 dB@100 Hz,功耗为3.7 nW。芯片面积为0.008 2 mm2。该电路适用于能量采集、无线传感器等低功耗应用。A high performance sub-threshold CMOS voltage reference was designed in a 0.18 μm CMOS process. A voltage subtraction circuit working in the sub-threshold region was proposed, which adopted the gate-source voltage difference of two transistors with different threshold voltages as the voltage reference output. At the same time, the proposed voltage subtraction circuit could well eliminate the influence of the power supply voltage change on the output reference. The post-simulation results showed that the voltage reference designed in this paper had a linear sensitivity of 0.053%/V~0.121%/V in the supply voltage range of 0.55~1.8 V, the temperature coefficient was 9.5×10^(-6)/℃~3.49×10^(-5)/℃ in the temperature range of-20 ℃~80 ℃, the power supply rejection ratio was-65 dB@100 Hz, and the power consumption was 3.7 nW @tt, 0.55 V. The chip area was 0.008 2 mm2. The circuit was suitable for low power applications such as energy harvesting and wireless sensors.

关 键 词：CMOS电压基准 电压减法电路 亚阈值区 低功耗应用 

分 类 号：TN432[电子电信—微电子学与固体电子学]