一种采用低阈值技术实现的高速采样保持电路  

A High Speed Sample and Hold Circuit Using Low Threshold Technology

作　　者：郭亮 曾涛 黄飞淋 雷郎成[1] 苏晨[1] 刘凡[1] 刘伦才[1] GUO Liang;ZENG Tao;HUANG Feilin;LEI Langcheng;SU Chen;LIU Fan;LIU Luncai(The 24th Research Institute of China Electronics Technology Group Corp.,Chongqing 400060,P.R.China)

机构地区：[1]中国电子科技集团公司第二十四研究所,重庆400060

出　　处：《微电子学》2021年第2期168-172,共5页Microelectronics

基　　金：模拟集成电路国家重点实验室基金资助项目(6142802010702)。

摘　　要：提出了一种采用低阈值技术实现的高速采样保持电路。采样保持电路采用电容翻转式架构,利用栅压自举开关技术提高了采样开关的线性度,通过下极板采样技术减小了电荷注入效应。提出的放大器与传统的套筒式共源共栅极放大器在电路结构上相同。不同点在于,该放大器采用了低阈值设计技术。优势在于,在特定工艺下通过低阈值器件补偿可实现高增益带宽放大器,提高了采样保持电路的采样速率。该电路采用0.18μm CMOS工艺设计并流片,采样时钟频率达到了125 MHz。仿真结果表明,SINAD为90.91 dB,SFDR为91.45 dBc,芯片尺寸为0.8 mm×0.5 mm。A high speed sample and hold(S/H) circuit using low threshold technology was presented. Capacitor flip-around architecture was used for S/H circuit. Gate-bootstrapped switch technique was used to improve linearity. Bottom-plate sampling technique was adopted to reduce charge injection effect. The proposed amplifier and the traditional telescopic common-source common-gate amplifier had the same circuit structure. What’s the difference was that the proposed amplifier used a low threshold technology with the advantages of high gain and bandwidth by adopting low threshold device compensation based on a specific process, and it improved the sampling rate of the sample-and-hold circuit. The circuit was designed and fabricated in a 0.18 μm CMOS technology, and the sampling clock frequency was more than 125 MHz. The simulation results showed that SINAD was 90.91 dB, SFDR was 91.45 dBc, and the chip area was 0.8 mm×0.5 mm.

关 键 词：采样保持电路 放大器 低阈值技术 

分 类 号：TN432[电子电信—微电子学与固体电子学]