一种低功耗低延迟的容忍DNU锁存器设计  

Design of a Low Power and Low Delay DNU-Tolerant Latch

作　　者：国欣祯 杨潇 郭阳 GUO Xinzhen;YANG Xiao;GUO Yang(School of Electronic Science and App lied Physics,Hefei University of Technology,Hefei 2300091 P.R.China)

机构地区：[1]合肥工业大学电子科学与应用物理学院,合肥230009

出　　处：《微电子学》2021年第2期203-210,共8页Microelectronics

基　　金：国家自然科学基金资助项目(61904047)。

摘　　要：随着集成电路器件特征尺寸的进一步减小,锁存器内部节点之间的距离越来越短。由于内部节点间的电荷共享效应,器件在空间辐射环境中频繁发生单粒子翻转(SEU),受影响节点由单节点扩展到双节点。文章提出了一种新型的锁存器加固结构,利用C单元固有的保持属性,实现对单节点翻转(SNU)和双节点翻转(DNU)的完全容忍。HSPICE仿真结果表明,相比于其他同类型的加固设计,所提出的锁存器功耗平均下降了34.86%,延迟平均下降了59%,功耗延迟积平均下降了67.91%。PVT分析表明,该锁存器结构对电压、温度、制造工艺的变化不敏感。As the feature size of the integrated circuit devices is reduced further, the distance among the internal nodes of the latch becomes shorter and shorter. Due to the charge sharing effect among internal nodes, single event upset(SEU) affected nodes that frequently occurred in the space radiation environment have expanded from single nodes to double nodes. A new hardened latch structure which used the inherent hold property of the C-element was proposed in this paper. A complete tolerance to single node upset(SNU) and double node upset(DNU) was realized. HSPICE simulation results showed that, compared with other similar hardened designs, the power consumption of the proposed latch had decreased by 34.86% on average, the delay had decreased by 59% on average, and the power delay product had decreased by 67.91% on average. PVT analysis showed that the proposed latch structure was not sensitive to the changes in voltage, temperature and manufacturing processes.

关 键 词：单粒子翻转 低功耗 低延迟 双节点翻转 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN406