基于FPGA的USB3.0通信接口设计  

Design of USB3.0 Communication Interface Based on FPGA

作　　者：刘林仙[1] 乔楠楠 童强 王朝阳 马奎 李升[1] 杨佳苗 LIU Linxian;QIAO Nannan;TONG Qiang;WANG Zhaoyang;MA Kui;LI Sheng;YANG Jiamiao(School of Automation and Software Engineering, Shanxi University, Taiyuan 030013, China;School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai 200240, China)

机构地区：[1]山西大学自动化与软件学院,山西太原030013 [2]上海交通大学电子信息与电气工程学院,上海200240

出　　处：《测试技术学报》2021年第3期261-265,共5页Journal of Test and Measurement Technology

基　　金：国家自然科学基金资助项目(61603231);山西省应用基础研究资助项目(201801D221166,201801D22172);山西省高等学校科技创新资助项目(2019L0068);山西省研究生教育创新资助项目(2020SY018)。

摘　　要：针对大批量高速数据传输的准确性和稳定性问题,本文设计了一种适用于FPGA开发使用的USB3.0通信IP核接口.采用Cypress公司的CYUSB3014芯片作为USB3.0器件,在vivado软件上进行USB3.0通信IP核接口的软件设计,最终在以FPGA作为主控芯片的USB3.0高速数据传输系统上对该IP核进行测试.测试结果表明,该IP核实际可达到的最大上行通信速率可达253.1 MB/s,下行最大通信速率可达131.9 MB/s.To achieve the accuracy and stability of high-speed data transmission in large quantities,this paper designs a USB3.0 communication IP core interface suitable for FPGA development.Cypress’s CYUSB3014 chip is used as USB3.0 device.The design of USB3.0 communication IP core interface is carried out by vivado software.the IP core is tested on USB3.0 high-speed data transmission system based on FPGA.The test results show that the IP core can actually achieve a maximum communication rate of 253.1 MB/s upstream and 131.9 MB/s downstream.

关 键 词：高速数据传输 FPGA USB3.0 CYUSB3014 IP核 

分 类 号：TN919.3[电子电信—通信与信息系统]