卷积编码及Viterbi译码的低时延FPGA设计实现  

Low-latency FPGA design and implementation of convolutional coding and Viterbi decoding

作　　者：张健[1] 吴倩文 高泽峰 周志刚 Zhang Jian;Wu Qianwen;Gao Zefeng;Zhou Zhigang(School of Electronic Information,Hangzhou Dianzi University,Hangzhou 310018,China)

机构地区：[1]杭州电子科技大学电子信息学院,浙江杭州310018

出　　处：《电子技术应用》2021年第6期96-99,共4页Application of Electronic Technique

摘　　要：针对毫米波通信的高速率和低时延设计要求,设计实现1/2码率(2,1,7)卷积码的低时延译码。采用高度并行优化实现框架、低延时的最小值选择方式,获得Viterbi硬判决译码算法的输出。利用基于Xilinx公司的Artix7-xc7a200t芯片综合后,译码器的数据输出延时约89个时钟周期,最高工作频率可达203.92 MHz。结果表明,该译码器可支持吉比特级的数据传输速率,实现了低延时、高速率的编译码器。Aiming at the high-speed and low-delay design requirements of millimeter wave communications,this paper designs low-delay decoding of convolutional codes with 1/2 code rate(2,1,7).A highly parallel optimization implementation framework and a low-latency minimum selection method are adopted to obtain the output of the Viterbi hard decision decoding algorithm.After synthesis using the Artix7-xc7a200t chip based on Xilinx,the data output delay of the decoder is about 89 clock cycles,and the highest operating frequency can reach 203.92 MHz.The results show that the decoder can support gigabit-level data transmission rates,and realizes a low-latency,high-rate codec.

关 键 词：毫米波通信 卷积码 VITERBI译码 system generator 

分 类 号：TN911.22[电子电信—通信与信息系统]