Enabling Variability-Aware Design-Technology Co-Optimization for Advanced Memory Technologies  

作　　者：Salvatore MAmoroso Plamen Asenov Jaehyun Lee Nara Kim Ko-Hsin Lee Yaohua Tan Yong-Seog Oh Lee Smith Xi-Wei Lin Victor Moroz 

机构地区：[1]Synopsys Europe,Ltd.,Glasgow,G38HB,UK [2]Synopsys Korea,Pankyoyeokro 235,Gyeonggi-do13494 South Korea [3]Synopsys Taiwan Co.,Ltd.,Chupei 302,Taiwan [4]Synopsys,Inc.,Mountain View,CA 94043 USA

出　　处：《Journal of Microelectronic Manufacturing》2020年第4期69-81,共13页微电子制造学报（英文）

摘　　要：This paper presents a TCAD-based methodology to enable Design-Technology Co-Optimization(DTCO)of advanced semiconductor memories.After reviewing the DTCO approach to semiconductor devices scaling,we introduce a multi-stage simulation flow to study the deviceto-circuit performance of advanced memory technologies in presence of statistical and process variability.We present a DRAM example to highlight the DTCO enablement for both memory and periphery.Our analysis demonstrates how the evaluation of different possible technology improvements and design combinations can be carried out to maximize the benefits of continuous technology scaling for a given set of manufacturing equipment.

关 键 词：DTCO Statistical Variability Process Variability Semiconductor Memories DRAM CMOS Scaling. 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]