625 MS/s、12 bit双通道时间交织ADC的设计研究  

Design research of 625 MS/s, 12 bit two-channel time interleaved ADC

作　　者：曹宇 苗澎[1] 黎飞[1] 王欢 Cao Yu;Miao Peng;Li Fei;Wang Huan(School of Information Science and Engineering,Southeast University,Nanjing 211100,China)

机构地区：[1]东南大学信息科学与工程学院,南京211100

出　　处：《电子测量与仪器学报》2021年第3期105-114,共10页Journal of Electronic Measurement and Instrumentation

基　　金：国家重点研发计划(2018YFB2003302)项目资助。

摘　　要：基于40 nm CMOS工艺,设计了一款625 MS/s、12 bit双通道时间交织模数转换器(ADC)。单通道ADC采用了前端无采保模块的流水线架构以降低系统功耗。系统采用了宽带高线性度前级驱动电路以及高速高精度栅压自举开关以保证交织系统的有效输入带宽。一种基于辅助通道的后台校正算法被用于校正通道间采样时间失配,该后台校正方法可适用于完全随机输入信号。芯片核心面积为0.69 mm2。后仿真结果表明,该625 MS/s、12 bit时间交织ADC在全速率下进行奈奎斯特采样,系统无杂散动态范围(SFDR)为67 dB,信号-失真噪声比(SNDR)为58.5 dB,功耗为295 mW,满足设计指标,证明了设计的有效性。A 625 MS/s, 12 bit two-channel time interleaved ADC is designed in 40 nm CMOS process. The single channel is pipeline ADC with no sample-and-hold-amplifier(SHA) front-end for low-power consumption. A wideband and high-linearity foreground input buffer and a high speed and high precision bootstrapped switch are used for ensuring the effective input bandwidth of the interleaved system. A background calibration algorithm based on reference channel is applied for sampling time mismatch calibration between channels. This background calibration method is appropriate for completely random input signals. The core area of the system is 0.69 mm2. The post-simulation results show that the 625 MS/s, 12 bit time interleaved ADC achieves 67 dB of SFDR and 58.5 dB of SNDR with the Nyquist sampling at full sampling speed, while its power consumption is 295 mW, which meets the design targets and confirms the effectiveness of the design.

关 键 词：时间交织 流水线ADC 栅压自举开关 采样时间失配 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN453