基于55nm工艺的MCU低功耗物理设计  

Low power physical design of MCU based on 55 nm process

作　　者：陈力颖[1,2] 罗奎 王浩 刘宏伟[1,2] 吕英杰[3] CHEN Li-ying;LUO Kui;WANG Hao;LIU Hong-wei;LYU Ying-jie(School of Electronics and Information Engineering,Tiangong University,Tianjin 300387,China;Tianjin Key Laboratory of Optoelectronic Detection Technology and Systems,Tiangong University,Tianjin 300387,China;Tianjin Pengxiang Huaxia Technology Co.,Ltd.,Tianjin 300450,China)

机构地区：[1]天津工业大学电子与信息工程学院,天津300387 [2]天津工业大学天津市光电检测技术与系统重点实验室,天津300387 [3]天津鹏翔华夏科技有限公司,天津300450

出　　处：《天津工业大学学报》2021年第3期77-82,共6页Journal of Tiangong University

基　　金：国家留学基金资助项目(201908120039);天津市研究生科研创新项目(2019YJSS019)。

摘　　要：为了降低芯片的功耗,提高芯片的性能和可靠性,在传统数字芯片物理设计流程基础上,提出一种新的低功耗物理设计方法,包括布局(Placement)阶段采用SAIF文件进行低功耗的协同优化,并在布局结果基础上,通过手动配置时钟单元摆放来减小缓冲单元插入的方式进行低功耗的时钟树设计。结果表明:通过新的低功耗设计可以大幅改善芯片功耗,在布局阶段,芯片功耗降为原来的90.6%,建立时间的最差违例值由-6.021降为-0.880;时钟树综合(clock tree synthesis,CTS)阶段,功耗优化效果显著,时钟网络功耗降为原来的73.1%,总功耗降为原来的86.2%;时序得到改善,建立时间的违例总条数降为原来的12.5%,总违例值降为原来的3.0%,保持时间的违例总条数降为原来的39.8%,总违例值降为原来的7.5%。In order to reduce the power consumption of the chip and improve the performance and reliability of the chip,a new low power physical design method is proposed based on the traditional digital chip physical design process,which includes the use of SAIF file in the placement stage for low-power collaborative optimization,and on the basis of the placement results,the design of low-power clock tree is carried out by manually configuring the clock cell placement to reduce the insertion of buffer.The results show that the chip power consumption can be greatly improved through the new low power design:in the stage of placement,the chip power consumption is reduced to 90.6%,and the worst violation value of setup is reduced from-6.021 to-0.880;in the clock tree synthesis stage,the power consumption optimization effect is significant,the power consumption of clock network is reduced to 73.1%,and the total power consumption is reduce to 86.2%.The time is improved,the total number of setup violations is reduced to 12.5%and the total violation value is reduced to 3.0%,the total number of hold violation is reduced to 39.8%and the total violation value is reduced to 7.5%.

关 键 词：数字集成电路 布局 时钟树综合 低功耗 协同优化 

分 类 号：TN492[电子电信—微电子学与固体电子学]