基于平面肖特基二极管的平衡式亚毫米波倍频器芯片  

Balanced Sub-millimeter Wave Frequency Doubler Chip Based on Planar Schottky Diode

作　　者：孟范忠[1] 毕胜赢 陈艳 周国[1] 方园[1] MENG Fan-zhong;BI Sheng-ying;CHEN Yan;ZHOU Guo;FANG Yuan(The 13th Research Institute of CETC,Shijiazhuang 050051,China)

机构地区：[1]中国电子科技集团公司第十三研究所,石家庄050051

出　　处：《微波学报》2021年第3期64-67,共4页Journal of Microwaves

基　　金：国家自然科学基金(62034003)。

摘　　要：基于标准的平面肖特基二极管单片工艺设计了一款平衡式亚毫米波倍频单片集成电路。依据二极管实际结构进行电磁建模,提取了器件寄生参数,并与实测的器件本征参数相结合获得了二极管非线性模型;依据该模型,采用平衡式拓扑结构以实现良好的基波抑制,设计了三线耦合巴伦电桥,并与肖特基二极管集成在同一芯片上,实现了单片集成,提高了设计准确度。芯片在片测试结果表明,在输入功率17 dBm下,输入频率75~105 GHz范围内,倍频器芯片峰值输出功率达到2.67 dBm。芯片整体尺寸为0.80 mm×0.50 mm。A balanced sub-millimeter wave frequency doubler monolithic microwave integrated circuit(MMIC) was designed based on standard planar Schottky diode process. The nonlinear model of the Schottky diode was established according to both the parasitic parameters, which was extracted from the electromagnetic(EM) model of the diode structure, and the measured intrinsic data. The frequency doubler used balanced topology to get good fundamental suppression, and a three-line coupled balun was designed and integrated with the Schottky diodes on one chip to improve the design accuracy. On chip test results show that when the input frequency varied from 75 GHz to 105 GHz, the frequency doubler chip could get 2.67 dBm peak power under 17 dBm input power. The chip size is only 0.80 mm×0.50 mm.

关 键 词：平面肖特基二极管 三线耦合巴伦 平衡式倍频器 单片集成电路 

分 类 号：TN771[电子电信—电路与系统] TN40