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作 者:何嘉文[1] 杜斐[1] 聂瞾 田泽[1] HE Jia-wen;DU Fei;NIE Zhao;TIAN Ze(AVIC Computing Technique Research Institute,Xi’an 710068,China)
机构地区:[1]航空工业西安航空计算技术研究所,陕西西安710068
出 处:《计算机技术与发展》2021年第8期129-133,共5页Computer Technology and Development
基 金:装备预研中航工业联合基金项目(6141B05060105)。
摘 要:当前芯片虚拟验证中,一般使用硬件描述语言(verilog语言或SystemVerilog语言)构建主机模型和验证平台,模拟主机行为,对待测设计施加激励。对于GPU芯片而言,由于芯片功能被拆分到软件驱动和硬件设计,且软件驱动功能极其复杂,导致利用硬件描述语言模拟软件驱动行为的主设备模型很困难,不仅开发时间较长,还难以确保主设备模型和软件驱动行为一致,且还需单独开发对软件驱动的验证平台。因此,该文提出了一种GPU芯片的软硬件协同验证平台构建方法,以SystemC语言作为桥梁,在虚拟验证平台中兼容软件语言开发的激励和驱动,以及使用硬件语言开发的待测设计,不仅能够加快GPU虚拟验证平台的开发进度,还能保证虚拟验证和芯片的测试时主设备模型行为的一致性,对当前GPU芯片验证工作很有帮助。In the current chip virtual verification,we usually use hardwire description language(verilog or SystemVerilog)to build master equipment model and verification platform,simulate the behavior of the master equipment,and exert incentives to the design under test.For GPU,because chip function is divided into software driver and hardwire design,and the function of the software driver is extremely complex,it is difficult to simulate the master equipment model of software driver behavior using hardware description language.In addition to the long development time,it is difficult to ensure that the master equipment model is consistent with the behavior of the software driver,and a verification platform for the software driver needs to be developed separately.Therefore,we propose a construction method of GPU software and hardwire cooperation virtual simulation platform.With SystemC language as a bridge,it is compatible with the motivation and driver of software language development and the design to be tested using hardware language development.This function not only speeds up the development of the simulation platform,but also ensures the consistency of the behavior of master equipment model during virtual verification and chip test,which is quite helpful to the current GPU chip verification.
关 键 词:虚拟验证平台 GPU芯片 软硬件协同 SYSTEMC 平台构建
分 类 号:TP39[自动化与计算机技术—计算机应用技术]
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