低寄生电感SiC MOSFETs模块的设计与制作  

Design and Manufacture of Low Parasitic Inductance SiC MOSFETs Modules

作　　者：王异凡 张斌 郭清 龚金龙 WANG Yi-fan;ZHANG Bin;GUO Qing;GONG Jin-long(Electric Power Research Institute,State Grid Zhejiang Electric Power Co.,Ltd.,Hangzhou 310024,China;不详)

机构地区：[1]国网浙江省电力有限公司,电力科学研究院,浙江杭州310024 [2]浙江大学,绍兴微电子研究中心,浙江绍兴312035

出　　处：《电力电子技术》2021年第8期141-144,共4页Power Electronics

基　　金：国网浙江省电力有限公司科技项目(5211DS18003B)。

摘　　要：为获得两芯片碳化硅金属氧化物半导体场效应晶体管(SiC MOSFETs)并联半桥模块的优化设计方案,采用Ansoft Q3D Extractor软件对不同互联拓扑结构的模块寄生电感进行研究,并通过ANSYS软件对不同互联拓扑结构的热传递过程进行了仿真。通过改变并联半桥模块内部换流回路中各元件的布局方式,减小模块内部换流通路的长度以及面积,从而实现减小寄生电感的目的,同时,也对不同方案的热学特性进行了比较分析。综合考虑寄生电感和散热性能两方面的因素,最终确定最优的模块设计方案;根据优化方案,针对电动汽车应用制作了6芯片并联半桥模块,并搭建Boost电路对模块进00行了测试。The working mechanism of a half-bridge silicon carbide metal oxide semiconductor field effect transistors(SiC MOSFETs)two chips parallel module is studied.Its parasitic inductance of the power module is simulated by using the Ansoft Q3 D Extractor software,and its heat transfer mechanism is simulated using the finite element software ANSYS software.Aiming at reducing the parasitic inductance,a new topology of power chips inside the module is designed,which places the chips that are in the same working circuit loop in close vicinity to reduce the whole circuit length and area.Mean while,the thermal characteristics are also analyzed.Considering the factors of parasitic inductance and heat dissipation,the optimal module design scheme is finally determined.According to the optimization scheme,a halfbridge module with 6 chips in parallel is made for and a Boost circuit is built to test the module.

关 键 词：金属氧化物半导体场效应晶体管 半桥 寄生电感 

分 类 号：TN304.21[电子电信—物理电子学]