基于40 nm CMOS工艺的电荷泵锁相环设计  

Design of charge pump phase-locked Loop based on 40 nm CMOS process

作　　者：路哲 马奎 唐重林 杨发顺 梁蓓[1,2] LU Zhe;MA Kui;TANG Zhonglin;YANG Fashun;LIANG Bei(School of Big Data and Information Engineering,Guizhou University,Guiyang 550025,China;Guizhou Key Laboratory of Micro/Nano Electronics and Software Technology,Guiyang 550025,China;Shanghai First Branch,Newcore Semiconductor(Shenzhen)Co.,LTD.,Shanghai 201210,China)

机构地区：[1]贵州大学大数据与信息工程学院,贵阳550025 [2]贵州省微纳电子与软件技术重点实验室,贵阳550025 [3]牛芯半导体(深圳)有限公司上海第一分公司,上海201210

出　　处：《智能计算机与应用》2021年第8期92-96,102,共6页Intelligent Computer and Applications

摘　　要：本文基于SMIC 40 nm CMOS工艺,设计了一款输入频率范围25~200 MHz,输出频率范围2.4~4 GHz的电荷泵锁相环(CPPLL)。介绍了电荷泵锁相环的整体电路框架,叙述了各子模块电路的设计、仿真验证与整体电路的设计与仿真验证,重点介绍压控振荡器的设计与仿真优化。版图后仿真结果表明,电荷泵电流失配在直流情况下达到0.3%@0.4-1.3 V;压控振荡器的输出频率范围为0.3~4 GHz、在输出频率1 MHz时相位噪声为-93.4 dB@1 MHz、锁定时间为1μs、绝对抖动为1 ps、典型值时的功耗为30 mW、面积为300×300μm。Based on THE SMIC 40nm CMOS process,a charge pump phase locked loop(CPPLL)with input frequency range of 25 MHz~200 MHz and output frequency range of 2.4 ghz~4 GHz is designed.This paper introduces the overall circuit frame of charge pump phase-locked loop,describes the design and simulation verification of each sub-module circuit and the overall circuit design and simulation verification,and focuses on the design and simulation optimization of vCO.The simulation results show that the loss distribution of charge pump reaches 0.3%@0.4-1.3 V under dc condition.The output frequency range of vCO is 300 MHz-4 GHz,the phase noise is-93.4 dB@1 MHz at the output frequency of 1 MHz,the locking time is 1μs,the absolute jitter is 1 ps,the power consumption is 30 mW at the typical value,the area is 300μm×300μm.

关 键 词：锁相环 相位噪声 抖动 鉴频鉴相器 低通滤波器 压控振荡 

分 类 号：TN46[电子电信—微电子学与固体电子学]