基板封装注塑中芯片断裂的有限元分析  

Finite Element Analysis of Die Crack in Molding Process of Laminate Substrate-Based Package

作　　者：顾骁[1] 宋健 顾炯炯[1] 李全兵 GU Xiao;SONG Jian;GU Jiongjiong;LI Quanbing(JCET Group Co.,Ltd,Wuxi 214437,China)

机构地区：[1]江苏长电科技股份有限公司,江苏无锡214437

出　　处：《电子与封装》2021年第9期25-31,共7页Electronics & Packaging

摘　　要：在基板封装注塑工序中,芯片有断裂风险。利用有限元方法建立封装模型,施加注塑压力载荷和约束条件,计算芯片在注塑压力下的应力云图。研究发现,芯片产生应力的主要原因为基板底面无阻焊层区域在注塑压力下发生了凹陷。基板增厚,芯片增厚,阻焊层减薄和注塑压力减小对应力有明显改善。此外,芯片与基板底面无阻焊层区的相对位置也是影响因素之一,芯片在基板底面无阻焊层区上方面积占比不宜过大,并尽量选择短边悬空,避免长边悬空,芯片整体悬空也有利于减小应力。In the molding process of laminate substrate-based package assembly,the die has risk of crack.The package model is built by finite element method,apply mold pressure loads and constraints,and calculate the stress of die under mold pressure.It is found that the main reason of the die stress is that the area with bottom solder mask openings will sag under mold pressure.Thicker substrate,thicker die,thinner solder mask thickness and smaller mold pressure can reduce die stress obviously.In addition,the relative position between chip and openings of back solder mask is also one of the main factors.Relative to the back solder mask openings,overhang ratio of die should not be excessive,and it's better to choose the short side of die to hang out,avoid long side to hang out,and the overall hanging of die can also help reduce the stress of die.

关 键 词：基板封装 芯片断裂 注塑压力 有限元分析 阻焊层 

分 类 号：TN305.94[电子电信—物理电子学]