Sigma-Delta模数转换器的三级数字抽取滤波器设计  

Design of Three-Stage Digital Decimation Filter for Sigma-Delta Analog-to-Digital Converter

作　　者：胥珂铭 高博[1] 龚敏[1] XU Keming;GAO Bo;GONG Min(College of Physics,Sichuan University,Chengdu 610065,China)

机构地区：[1]四川大学物理学院,成都610065

出　　处：《电子与封装》2021年第9期51-56,共6页Electronics & Packaging

摘　　要：提出了一种高精度、低资源消耗的Sigma-Delta模数转换器(Analog-to-Digital Converter,ADC)的数字抽取滤波器结构。该滤波器分为三级,整体降采样率为32,由锐化积分梳状级联滤波器(Sharpen Cascaded Integrator-Comb Filter,SCIC Filter)、有限长单位冲激响应滤波器(Finite Impulse Response Filter,FIR Filter)、半带滤波器(Half Band Filter,HB Filter)组成。该滤波器还使用了乘法器复用的结构,可以减少乘法器数量,设计中只使用了4个乘法器,节约了大量现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)板资源。滤波器使用MATLAB设计参数,Verilog HDL编写代码,使用Quartus软件进行板级综合设计,最终该设计比普通设计节省了26.3%的逻辑单元和15.6%的寄存器资源。使用MATLAB设计的五阶反馈调制器模型输出250 kHz信号,调制器理想信噪比(Signal-Noise Ratio,SNR)为149 dB,最终滤波器输出SNR达到134 dB。A high precision and low resource consumption sigma-delta analog-to-digital converter(ADC)digital decimation filter structure is proposed.The filter is divided into three levels with an overall down sampling rate of 32.It is composed of sharpen cascaded integrator-comb(CIC)filter,finite impulse response(FIR)filter and half band(HB)filter.The reuse of multipliers is used in the filter,which can greatly reduce the number of multipliers.Only four multipliers are used in the design,and greatly saves FPGA resources.MATLAB design parameters are used for the filter,realized with Verilog HDL code,Quartus software is used for board level synthesis,compared with the common design,the design saves 26.3%logic elements and 15.6%registers.The fifth-order feedback modulator model designed by MATLAB outputs 250 kHz signal.The ideal signal-noise ratio(SNR)of the modulator is 149 dB,and the final filter output SNR is 134 dB.

关 键 词：SIGMA-DELTA模数转换器 数字抽取滤波器 高精度 低资源消耗 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN47