基于FPGA的可配置卷积结构的神经网络协处理器设计  

FPGA-Based Configurable Convolutional Neural Network Co-Processor Design

作　　者：许庚林 冉峰[1] 郭爱英[1] 李娇[1] XU Genglin;RAN Feng;GUO Aiying;LI Jiao(Microelectronics Research and Development Center, Shanghai University, Shanghai 200444, China)

机构地区：[1]上海大学微电子研究与开发中心,上海200444

出　　处：《复旦学报（自然科学版）》2021年第4期482-491,共10页Journal of Fudan University：Natural Science

基　　金：上海市科学技术委员会重大基础项目(18JC1410402,16JC1400602);上海市科学技术委员会项目(17DZ2281700)。

摘　　要：针对卷积神经网络中卷积计算时间复杂度高、同一电路计算不同尺寸卷积造成资源浪费的问题,本文提出一种具有可切换卷积计算结构的神经网络协处理器.协处理器由32位的专用指令控制,通过对不同结构神经网络的解析,生成相应的控制指令.卷积计算单元根据指令自动切换乘累加器结构或乘加树结构,对多个卷积计算单元进行组合提高了电路的并行性.数据存储采用多级缓存策略,设计长条形寄存器进行多尺寸卷积窗口的数据缓存.在ZYNQ XC7Z020 FPGA上通过实验表明,该协处理器在100 MHz频率下运算性能达到10.80 GOPS,能效比达到14.59 GOPS/W,达到同类产品的主流水平.In view of the high complexity of convolution operation time in convolutional neural networks,and the waste of resources caused by the calculation of different size convolutions in the same circuit,this paper proposes a neural network coprocessor with a switchable convolution calculation structure.The coprocessor is controlled by 32-bit special instructions,and generates corresponding control instructions through the analysis of neural networks of different structures.The convolution calculation unit automatically switches to a multiply-accumulator structure or a multiply-accumulate tree structure according to the instruction,and the combination of multiple convolution calculation units improves the parallelism of the circuit.Data storage using a multi-level cache strategy,a two-level buffer register is designed to move the convolution window.Experiments on ZYNQ XC7Z020 FPGA show that the coprocessor has a computing performance of 10.80 GOPS and an energy efficiency ratio of 14.59 GOPS/W at a frequency of 100 MHz,reaching the mainstream level of similar products.

关 键 词：卷积神经网络 可编程逻辑器件 硬件加速 

分 类 号：TP338[自动化与计算机技术—计算机系统结构]