Ballet密码算法的FPGA优化实现  

Optimized FPGA Implementation of Ballet Cryptographic Algorithm

作　　者：陈心宇 李莉[1] 李泽群 CHEN Xinyu;LI Li;LI Zequn(Beijing Electronic Science and Technology Institute,Beijing 100070,P.R.China)

机构地区：[1]北京电子科技学院,北京市100070

出　　处：《北京电子科技学院学报》2021年第3期21-26,共6页Journal of Beijing Electronic Science And Technology Institute

基　　金：北京市共建项目专项资助。

摘　　要：通过分析分组密码算法Ballet的加解密过程,对Ballet算法的FPGA实现进行优化。对于单组数据加解密,提出一种分组迭代和密钥生成并行执行的实现方案,优化后单组数据在5ns时钟约束下加解密速率可以达到522.4Mbps;多组数据的快速加解密采用46级流水线实现方案,算法呑吐量可达27.2Gbit/s,能够满足大量数据的快速加解密操作的需求。By analyzing the encryption and decryption process of the Ballet block cipher algorithm,FPGA implementation of the Ballet algorithm is optimized.For the encryption and decryption of a single data group,an implementation scheme of grouping iteration and key generation parallel execution is proposed.With the optimization,the encryption and decryption rate of a single data group could achieve 522.4Mbps under the constraint of a 5ns clock.The fast encryption and decryption of multiple data groups adopt a 46-level pipeline implementation scheme,and the algorithm throughput could reach 27.2Gbit/s,which meets the requirements for the fast encryption and decryption of large amounts of data.

关 键 词：分组密码 Ballet算法 流水线 FPGA实现 硬件实现 

分 类 号：TN918.4[电子电信—通信与信息系统]