千兆以太网收发器芯片测试技术研究  

Research on Testing Technique of Integrated Gigabit Ethernet Transceiver

作　　者：武新郑 李斌 Wu Xin-zheng;Li Bin(China Key System&Integrated Circuit CO.,LTD.,Jiangsu Wuxi 214072)

机构地区：[1]中科芯集成电路有限公司,江苏无锡214072 [2]中科芯集成电路有限公司检测事业部,江苏无锡214072

出　　处：《电子质量》2021年第10期22-26,共5页Electronics Quality

摘　　要：千兆以太网收发器芯片是一款典型的高速数字类接口芯片,其数据速率支持10/100 Mbps,最高支持1000 Mbps的数据传输。该文对该芯片的测试研究,以在ATE测试机台上最终实现芯片各种模式下的功能为研究目标,开展对芯片工作模式、硬件配置、寄存器配置、数据采集等的测试方案研究。功能以回环的方式进行测试,高速数据接口上的信号不是该文重点研究对象,所以不涉及差分电压、抖动等参数的测试。为满足最高1000 Mbps的功能测试,时钟信号最高可达125 MHz,ATE测试机台需选用满足至少500 MHz带宽的数字通道资源。The Gigabit Ethernet Transceiver chip is a typical high-speed digital interface chip with data rates of 10 M/100 Mbps,which can be up to 1,000 Mbps.in this paper,We do the test on the ATE test bench to Realize the function of the chip in various modes.We do research on the test scheme of chip working mode,hardware configuration,register configuration,data acquisition,etc.The function is tested in a return loop manner,the signal on the high speed data interface is not focused in this paper,so it does not involve the test of differential voltage,jitter and other parameters.To meet a feature of up to 1,000 Mbps,to guarantee the clock signal be up to 125 MHz,the ATE test bench shall select digital channel resources with at least 500 MHz bandwidth.

关 键 词：千兆以太网收发器芯片 功能 回环 ATE 

分 类 号：TN929.11[电子电信—通信与信息系统]