基于MIPI规范的从端D-PHY数字电路设计  

Design of slave D-PHY digital circuit based on MIPI specification

作　　者：张自豪 赵建中[1] 周玉梅[1,2] Zhang Zihao;Zhao Jianzhong;Zhou Yumei(Institute of Microelectronics,Chinese Academy of Science,Beijing 100029,China;University of Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院大学,北京100049

出　　处：《电子技术应用》2021年第11期33-38,共6页Application of Electronic Technique

基　　金：国家科技重大专项02专项(2016ZX02301)。

摘　　要：基于MIPI D-PHY v1.1规范,提出了一种从端D-PHY数字电路设计,该从端D-PHY采用4通道实现。高速模式下,单通道数据传输速率最高支持1.5 Gb/s;低功耗模式下,通道0数据传输速率最高支持10 Mb/s。高速模式下,串行数据流的解串由模拟电路实现,解串后数据的帧头同步检测由数字电路实现;D-PHY引导码的检测以及低功耗模式下数据传输为异步通信,提出了一种异步时钟实现方式;采用SMIC 0.18μm CMOS工艺库进行综合,典型工艺角下,整体电路的面积为95061μm^2;整体功耗为4.291 mW,其中低功耗模式下功耗为231.3μW。Based on the MIPI D-PHY version 1.1 specification,a design of slave D-PHY digital circuit is proposed,which is implemented with 4 lanes.In the high-speed mode,the data transfer rate of a single lane supports up to 1.5 Gb/s;in the low-power mode,the data transfer rate of lane 0 is up to 10 Mb/s.In the high-speed mode,the deserialization of the serial data stream is implemented by the analog circuit,and the synchronization detection of the data frame header after deserialization is realized by the digital circuit;the detection of the D-PHY entry code and the data transmission in the low-power mode are asynchronous communication and a kind of asynchronous clock implementation is proposed;SMIC 0.18μm CMOS process library is used for synthesis,and at the typical process corner,the overall circuit area is 95061μm^2;the overall power consumption is 4.291 mW,and the power consumption in low power mode is 231.3μW.

关 键 词：MIPI D-PHY 高速模式 低功耗模式 异步时钟 

分 类 号：TN492[电子电信—微电子学与固体电子学]