自适应定阶的快速Burg算法设计与FPGA实现  

Design and FPGA implementation of fast Burg algorithm of adaptive order determination

作　　者：郭鸣晗 陈立平[2] 张浩[2] 赵坤[2] 柏伟 Guo Minghan;Chen Liping;Zhang Hao;Zhao Kun;Bai Wei(University of Chinese Academy of Sciences,Beijing 100049,China;Institute of Microelectronics of Chinese Academy of Sciences,Beijing 100029,China)

机构地区：[1]中国科学院大学,北京100049 [2]中国科学院微电子研究所,北京100029

出　　处：《电子技术应用》2021年第11期62-67,72,共7页Application of Electronic Technique

基　　金：国家重点研发计划项目(2020YFC2003304)。

摘　　要：针对信号频谱分析的实时性要求,设计了一种适用于短序列的自适应定阶的快速Burg算法硬件加速电路。以FPGA为平台进行实验,将快速Burg算法与最终预测误差(Final Prediction Error,FPE)准则结合可做到自回归(Auto-Regressive,AR)参数自适应定阶。实现了灵活控制的并行二级流水线结构和并行化计算单元,同时优化了存储单元,达到速度与面积的平衡。实验结果表明,该算法对短序列也能准确地估计信号频率,与Burg算法硬件实现方案的计算时间对比,该算法将运算时间降低了75%,确实起到了加速作用,并且节省了内存空间,符合设计要求。Aiming to real-time requirement of signal spectrum analysis,an adaptive ordering of fast Burg algorithm hardware acceleration circuit for short sequence based on FPGA is designed.The fast Burg algorithm combined with FPE criterion can be used to determine the order of AR parameters.The parallel two-stage pipeline structure with flexible control is realized,and the parallel computing unit is parallelized.At the same time,the storage unit is optimized to achieve the balance between speed and area.The test show that the algorithm can accurately estimate the signal frequency for short sequences.Compared with the calculation time of Burg algorithm hardware implementation scheme,this algorithm reduces the calculation time by 75%,which does play a role of acceleration,and saves memory space.So,this design meets the design requirements.

关 键 词：AR参数模型 Burg算法 快速Burg算法 FPGA 硬件加速 

分 类 号：TN911.72[电子电信—通信与信息系统] TN4[电子电信—信息与通信工程]