基于SiP封装的DDR3时序仿真分析与优化  

Timing simulation analysis and optimization of DDR3 based on SiP package

作　　者：王梦雅 曾燕萍 张景辉 周倩蓉 Wang Mengya;Zeng Yanping;Zhang Jinghui;Zhou Qianrong(China Electronic Technology Group Corporation No.58 Research Institute,Wuxi 214035,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《电子技术应用》2021年第10期42-47,共6页Application of Electronic Technique

摘　　要：针对DDR3系统设计对时序要求的特殊性,对某一SiP(System in Package)中DDR3封装和基板设计进行时序仿真和优化,通过仿真指导设计,提高SiP产品DDR3的设计成功率,减少设计周期。通过ANSYS SIwave软件提取信号S参数,再经过Cadence SystemSI软件搭建拓扑进行时序仿真分析,利用信号完整性相关理论,讨论信号时序与波形的关系,结合版图分析,给出实际的优化方案,并经过仿真迭代验证,最终使所设计的DDR3满足JEDEC协议中的时序要求。Aiming at the timing requirements of DDR3 system,timing simulation and optimization were carried out for DDR3 package and substrate design in a SiP(System in Package).Through simulation guidance design,the design success rate of DDR3 in SiP product was improved and the design cycle was reduced.The signal scattering parameters were extracted by ANSYS SIwave software,and then the topology construction and timing simulation analysis was carried out through Cadence SystemSI software.The relationship between signal timing and waveform was discussed based on the theory of signal integrity.The actual optimization scheme was given by combining with layout analysis.Finally,the designed DDR3 system could meet the timing requirements of JEDEC protocol through simulation iteration verification.

关 键 词：DDR3 系统级封装(SiP) 时序仿真 高密度互连 信号完整性 

分 类 号：TN405.97[电子电信—微电子学与固体电子学]