“数字逻辑电路”课程中时延及时序问题的讨论  

作　　者：王华东[1] 晏中华 何丰[1] 

机构地区：[1]重庆邮电大学光电工程学院,重庆400065

出　　处：《课程教育研究》2021年第8期136-138,共3页Course education research

基　　金：重庆邮电大学教育教改项目(项目编号:XJG19207)。

摘　　要：逻辑器件的延迟问题在传统数字电路课程中通常是被忽略的内容,但在现代数字逻辑电路设计过程中,逻辑器件的传输延迟及相关时序问题已经成为电路设计的关键。本文探讨了数字逻辑电路课程中引入时延及时序问题的必要性,并在实际的数字电路课程教学过程中进行试点,最终对试点结果进行了分析总结。Delay of the logical devices has usually been neglected in traditional digital logical circuits course.However,it and relevant timing analysis problem play more important roles than before in current logical circuit design process.In this paper,the necessary of adding logical devices delay and timing analysis problem in digital logical circuit course is discussed,and actual teaching process of the delay and time constraints in logical circuits course is introduced.At the end of the paper,the conclusion of the attempt is given.

关 键 词：数字逻辑电路 时延 时序约束 

分 类 号：TN79[电子电信—电路与系统]