一种集成4/5和8/9的异步预分频器设计  

The design of asynchronous prescaler integrated with 4/5 and 8/9 dividers

作　　者：张博 王好博 ZHANG Bo;WANG Haobo(School of Electronic Engineering,Xi􀆳an University of Posts and Telecommunications,Xi􀆳an710121,China)

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121

出　　处：《电子元件与材料》2021年第11期1123-1128,1134,共7页Electronic Components And Materials

基　　金：陕西省教育厅服务地方产业化专项(15JF029);陕西省重点研发计划项目(2018ZDXM-GY-010,2017ZDXM-GY-004,2016KTCQ01-08);西安市集成电路重大专项(201809174CY3JC16)。

摘　　要：为了提高频率综合器的性能,基于源极耦合逻辑(Source Coupled Logic)电路设计了一种集成4/5分和8/9分的异步预分频器。通过分析SCL电路结构的工作原理和触发器的不同电路结构,在不降低电路工作频率和不增大电路功耗的前提下,利用模式控制电路和传输门将4/5分频器和8/9分频器集成在一个电路中,拓宽了分频器的输出分频范围。基于TSMC 0.18μm CMOS工艺,利用Cadence Spectre工具进行仿真。该预分频器在电源电压为1.8 V,尾电流源为50μA的条件下,电路最高工作频率可达8 GHz,功耗仅为6 mW。In order to improve the performance of frequency synthesizer,an asynchronous prescaler integrated with the 4-or-5 and 8-or-9 dividers was designed based on the source coupled logic circuit.Based on the working principle of SCL circuit and the different circuit structure of D-flip-flop,the 4-or-5 divider and the 8-or-9 divider were integrated into one circuit,to broaden the output division range through the joint effects of transmission gate circuit and the mode control circuit was broadened under the condition of same circuit performance frequency and power consumption.This circuit was simulated by Cadence Spectre under the CMOS technology of TSMC 0.18μm.The experiment result shows that the maximum operating frequency of the prescaler can be up to 8 GHz under the condition of 1.8 V supply voltage and 50μA tail current,while its power consumption is only 6 mW.

关 键 词：源极耦合逻辑 异步分频器 D触发器 CMOS工艺 

分 类 号：TN722[电子电信—电路与系统]