数字电子钟的设计及其VHDL实现  

VHDL Design and Realization of Digital Electronic Clock

作　　者：黄卫华[1] HUANG Weihua(Guangxi Technological College of Machinery and Electricity,Nanning 530007,China)

机构地区：[1]广西机电职业技术学院,南宁530007

出　　处：《装备制造技术》2021年第9期177-179,228,共4页Equipment Manufacturing Technology

摘　　要：使用VHDL语言代码进行电路设计已经成为电子系统设计的趋势和主流。采用两种不同的设计思路对数字钟进行了VHDL设计,并对同步计数和异步计数的设计思路及其VHDL代码进行了比较分析。结果表明,两种VHDL代码下载到FPGA芯片中均可以实现数字钟计时和调时的功能。Using VHDL language code for circuit design has become the trend and mainstream of electronic system design.This paper uses two different design ideas of digital clock VHDL design,and synchronous counting and asynchronous counting design ideas and their VHDL code are compared and analyzed.The results show that the two VHDL codes downloaded to FPGA chip can realize the digital clock timing and adjusting.

关 键 词：VHDL 数字钟 同步 异步 

分 类 号：U239.5[交通运输工程—道路与铁道工程]