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作 者:周宇[1] 陈宇[1] 高洪艺 李成敏[1] 罗皓泽[1] 李武华[1] 何湘宁[1] ZHOU Yu;CHEN Yu;GAO Hongyi;LI Chengmin;LUO Haoze;LI Wuhua;HE Xiangning(College of Electrical Engineering,Zhejiang University,Hangzhou 310027,Zhejiang Province,China)
机构地区:[1]浙江大学电气工程学院,浙江省杭州市310027
出 处:《中国电机工程学报》2022年第1期260-270,共11页Proceedings of the CSEE
基 金:国家杰出青年科学基金项目(51925702);国家自然科学基金项目(51677166);浙江省自然科学基金项目(LQ21E070006)。
摘 要:数值优化为功率半导体模块实现低感与均流设计提供了灵活有效的新途径,但同时也对模块整体与分布电感的评估效率提出了更高要求。为了适应寻优计算需求,基于部分元等效电路(partial element equivalent circuit,PEEC)理论,提出一种基于多端口网络模型的功率模块布局电感快速提取方法。该方法通过构建与芯片导通状态无关的多端口网络模型,从而将模块整体和分布电感的提取问题由多次大规模PEEC求解转化为单次预处理分解加端口网络求解。此外,为减少微元数量,针对模块线路的平面注入结构,对键合线、金属层直行区和注入区使用分区域离散策略。算例分析和实验验证表明,所提方法计算误差小于5%,满足工程应用需求,计算时间相比ANSYSQ3D软件减少85%以上,适合用于功率模块的快速寻优设计。Numerical optimizations provide a new flexible and effective approach for the design of low-inductance and current-balance power modules,but meanwhile they set stricter requirements for efficiency of module inductance evaluations.To meet the demand of large-scale searches,based on the partial element equivalent circuit(PEEC)theory,a fast inductance extraction method with a multi-port network model was proposed.The method used the multi-port network model that was irrelevant to chip status to transform the problem of extracting overall and distribute inductances of the power module from multiple times solving of PEEC to a single-time decomposition of the circuit and solving of the port network.Besides,considering the plane and injection structure of layouts,a multi-block discretization strategy was proposed for wires and traces in straight and injection areas to reduce the filament quantity.The numerical and experimental results show that the calculation error of the method is less than 5%,which satisfies the need of engineering application,and the calculation time is reduced over 85%compared with the ANSYS Q3D software,made it suitable for fast optimization of power modules.
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