应用于格密码的可重构多通道数论变换硬件设计  

Reconfigurable Hardware Design of Multi-lanes Number Theoretic Transform for Lattice-based Cryptography

作　　者：刘冬生[1] 赵文定 刘子龙 张聪[1] 刘星杰 LIU Dongsheng;ZHAO Wending;LIU Zilong;ZHANG Cong;LIU Xingjie(School of Optical and Electronic Information,Huazhong University of Science and Technology,Wuhan 430074,China)

机构地区：[1]华中科技大学光学与电子信息学院,武汉430074

出　　处：《电子与信息学报》2022年第2期566-572,共7页Journal of Electronics & Information Technology

基　　金：国家自然科学基金(61874163);国家科技重大专项基金(2017ZX01032-101);中央高校基本科研基金(HUST:2018KFYYXJJ056)。

摘　　要：针对不同格密码体制带来的数论变换参数多样性,以及数论变换的性能优化设计,该文提出一种基于随机存取存储器(RAM)的可重构多通道数论变换单元。在数论变换单元设计中,在按时间抽取的基础上改进多通道架构,并提出一种优化地址分配方法。最后基于Xilinx Artix-7现场可编程逻辑门阵列(FPGA)平台进行原型实现,结果显示,所设计的数论变换单元消耗的资源为1744 Slices, 16 DSP,完成1次多项式乘法的时间为2.01μs(n=256), 3.57μs(n=512), 6.71μs(n=1024)和13.43μs(n=2048),支持256~2048的不同参数n和13~32 bit模q的可重构配置,工作频率最高可达232 MHz。The performance of number theoretic transformation in lattice-based cryptography is insufficient, and the number theoretic transformation parameters are different. A Random Access Memory(RAM)-based reconfigurable multi-lanes number theoretic transform is proposed. In the design of number theory transformation unit, the multi-lanes architecture is improved on the time decimation operation architecture,and an optimized address allocation method is proposed. The number theory transform unit is implemented on Xilinx artix-7 Field Programmable Gate Array(FPGA) platform. The results show that the resource consumed by the unit is 1744 slices and 16 DSP, and the time to complete a polynomial multiplication is 2.01 μs(n=256),3.57 μs(n=512), 6.71 μs(n=1024) and 13.43 μs(n=2048). The unit supports reconfigurable configurations of 256~2048 parameters n and 13~32-bit modulus q, and the maximum operating frequency is 232 MHz.

关 键 词：格密码 多项式乘法 数论变换 硬件实现 

分 类 号：TN918.2[电子电信—通信与信息系统] TN402[电子电信—信息与通信工程]