基于FPGA的CRC编解码算法研究  

A Study on CRC Coding and Decoding Algorithm Based on FPGA

作　　者：李世伟 马家庆 LI Shiwei;MA Jiaqing(The Electrical Engineering College,Guizhou University,Guiyang 550025,China)

机构地区：[1]贵州大学电气工程学院,贵阳550025

出　　处：《微处理机》2022年第1期18-21,共4页Microprocessors

摘　　要：为抵抗复杂传输环境对通信数据造成的影响,对循环冗余校验码CRC这一通信系统中常用的差错控制技术展开研究,设计一套算法在软硬件层面深入挖掘CRC的潜力。在简介循环冗余校验基本原理的基础上,以国际标准CRC-16为研究对象,分析编码和解码过程,在Quartus II上开发平台,运用Verilog硬件描述语言实现CRC的编码与解码。采用Modelsim软件进行仿真验证,结果表明所设计算法的正确性。算法基于可编程硬件技术实现CRC编码与解码,具有运行速度快、容易迁移的优点。In order to resist the influence of complex transmission environment on communication data, the cyclic redundancy check code(CRC), a commonly used error control technology in communication system, is studied, and a set of algorithms is designed to tap the potential of CRC at the hardware and software level. On the basis of introducing the basic principle of CRC, taking the international standard CRC-16 as the research object, coding and decoding process is analyzed, a platform on Quartus II is developed, and the coding and decoding of CRC is realized through using Verilog hardware description language. The Modelsim tool is used for simulation verification, and the results show that the designed algorithm is correct. CRC coding and decoding based on algorithmic programmable hardware technology has the advantages of fast running speed and easy migration.

关 键 词：现场可编程门列阵 循环冗余校验码 VERILOG硬件描述语言 差错控制 

分 类 号：TN911.22[电子电信—通信与信息系统]