集成电路测试系统高速数字通道校准装置架构设计  

Architecture Design of High-speed ATE Calibration Device

作　　者：胡勇 黄俊杰 姚俊杰 HU Yong;HUANG Junjie;YAO Junjie(th Research Institute of China State Shipbuilding Corporation,Wuhan 430205)

机构地区：[1]中国船舶集团有限公司第七○九研究所,武汉430205

出　　处：《舰船电子工程》2022年第2期161-164,共4页Ship Electronic Engineering

摘　　要：数字通道测试速率的不断提升以及单块板卡的集成度越来越高是当今大规模集成电路(SOC)测试系统发展的趋势,由于测试系统高速数字通道校准的特殊性以及缺少对高速数字通道校准方法及技术规范的研究,当前高速数字通道普遍缺乏可靠的量值溯源途径。论文提出了一种集成电路测试系统高速数字通道校准装置架构设计方法,该方案具备一定的创新性,可以实现校准装置的通用性、便携性以及校准过程的自动化。The calibration of Automated Test Equipment(ATE)is an important part of microelectronics measurement. To achieve full calibration of high-speed ATE,each high-speed digital channel should be traced to the calibration equipment. Calibrating each channel individually with an instrument will pose a great challenge to the calibration of ATE,and channel switching will increase a large amount of calibration time. This paper puts forward a design solution of calibration device of high-speed ATE,which can realize the versatility and portability of calibration equipment,and realize multichannel automatic calibration progress.

关 键 词：集成电路测试系统 高速 校准 

分 类 号：TN4[电子电信—微电子学与固体电子学]