基于MIPI D-PHY规范的低速接收电路设计  

Design of low-speed receiving circuit based on MIPI D-PHY specification

作　　者：张自豪 赵建中[1] 周玉梅[1,2] ZHANG Zihao;ZHAO Jianzhong;ZHOU Yumei(Institute of Microelectronics,Chinese Academy of Science,Beijing 100029,China;University of Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院大学,北京100049

出　　处：《电子设计工程》2022年第5期37-41,共5页Electronic Design Engineering

摘　　要：文中基于MIPI D-PHY 1.1规范,提出了一种低速接收电路。该低速接收电路通过线路电平产生内部异步低速时钟,进行引导码的检测;在ESC;MD和LPDT状态下,通过Spaced-One-Hot解码电路产生进入命令码和低速有效数据。搭建了D-PHY模拟电路模型,在TestBench平台上仿真验证了低速模式下LPDT、Trigger和ULPS模式之间的进入和退出测试用例。分析DC逻辑综合时序报告,该低速模式接收电路满足D-PHY 1.1规范的数据速率要求。Based on the MIPI D-PHY version 1.1 specification,a low-speed receiving circuit is propsed.The low-speed receiving circuit generates an internal asynchronous low-speed clock via line level to detect the entry code;in ESC_CMD and LPDT states,the entry command code and low-speed valid data are generated by the Spaced-One-Hot decoding circuit. A D-PHY analog circuit model is built,and the entry and exit test cases between LPDT,Trigger and ULPS modes in low-speed mode are simulated and verified on the TestBench platform. Analysis of the DC logic synthesis reports show that the low-speed receiving circuit meets the data rate requirements of the D-PHY version 1.1 specification.

关 键 词：MIPI D-PHY 低速时钟 Spaced-One-Hot LPDT模式 

分 类 号：TN492[电子电信—微电子学与固体电子学]