32位RISC-V处理器中乘法器的优化设计  

Optimization design of multiplier in 32-bit RISC-V processor

作　　者：唐俊龙[1,2] 汤孟媛 吴圳羲 卢英龙 邹望辉 TANG Junlong;TANG Mengyuan;WU Zhenxi;LU Yinglong;ZOU Wanghui(School of Physics&Electronic Science,Changsha University of Technology&Sicence,Changsha 410114,China;Key Laboratory of Flexible Electronic Material Genetic Engineering of Hunan Province,Changsha 410114,China)

机构地区：[1]长沙理工大学物理与电子科学学院,湖南长沙410114 [2]柔性电子材料基因工程湖南省重点实验室,湖南长沙410114

出　　处：《电子设计工程》2022年第6期61-65,共5页Electronic Design Engineering

基　　金：柔性电子材料基因工程湖南省重点实验室开放基金(202015)。

摘　　要：针对32位RISC-V“蜂鸟E203”处理器的乘法器部分积压缩延时较大的问题,该文改进5-2压缩器,提出一种由新型5-2压缩器和4-2压缩器相结合的Wallace树形压缩结构,压缩基4 Booth编码产生的部分积,提高部分积压缩的压缩效率,优化设计出一种改进的32位有/无符号乘法器,减少乘法指令执行周期和乘法器关键路径延时,提高乘法器的运算速度。利用Modelsim仿真验证了乘法器功能的正确性。基于SIMC 180 nm工艺,采用Synopsys的Design Compile工具进行综合处理,结果表明,单次乘法指令执行周期减少了88.2%,关键路径延时为2.43 ns。The problems that delay of the partial product compression of the multiplier in 32-bit RISC-V "Hummingbird E203" processor is larger. In this paper,a new 5-2 compressors is designed,and new Wallace tree structure is put forwardby the combination new type of 5-2 compressors and 4-2 compressorsto compress the partial product which is created by4 Booth encoding. Compression efficiency is improved with the structure.A 32-bit multiplier with/without symbols is optimizated and designd base on thenew Wallace tree structure to reduce execution cycle of the multiplication instruction and critical path delay of the multiplier.Operation speed of the multiplier has been improved. The multiplier is simulated and verified by Modelsim tool,and the functions are correct. Synthesis of the multiplier with SIMC 180 nm process based on Synopsys Design Compile tool is completed. The results show that the execution cycles of single multiplication instruction are reduced by 88.2%,and the critical path delay is 2.43 ns.

关 键 词：RISC-V处理器 乘法器 压缩器 BOOTH编码 

分 类 号：TN492[电子电信—微电子学与固体电子学]