基于Sigrity在SDIO板级信号完整性仿真分析与优化  

Simulation and Analysis of Signal Integrity at the SDIO Board Level Based on Sigrity

作　　者：王楚哲 苏成悦[1] 李增 陈洪极 吴艳杰[1] 李红涛[1] WANG Chuzhe;SU Chengyue;LI Zeng;CHEN Hongji;WU Yanjie;LI Hongtao(School of Physics and Optoelectronic Engineering,Guangdong University of Technology,Guangzhou 510006,China)

机构地区：[1]广东工业大学物理与光电工程学院,广州510006

出　　处：《计算机测量与控制》2022年第3期204-210,221,共8页Computer Measurement &Control

摘　　要：随着高集成度集成电路与高速板级印制电路的发展,板间通信频率已经达到GHz水平,传统板级电路设计方案已经无法普及到更高频率的电路设计;针对高速SDIO总线在板级的设计,基于Cadence Sigrity平台的信号完整性仿真,提出了一种针对SDIO总线的高速信号仿真方法,该方法对SDIO总线有较高的仿真参考意义,通过海思Hi3516EV200嵌入式平台的板级电路设计与仿真优化,对层叠结构、层叠顺序、走线长度、地过孔、过孔数目实验仿真,优化PCB设计,对S参数与时域图进行研究与分析,提出了一种SDIO总线的电路走线设计参考方法,通过理论分析与仿真实验论证了该方案的可行性与实用价值,填补了信号完整性仿真分析中对SDIO总线设计的空白。With the development of highly integrated circuits and high-speed board-level printed circuits,the communication frequency between boards has reached the GHz level,and the traditional board-level circuit design scheme has been unable to popularize the circuit design of higher frequencies.Aiming at the board-level design of the high-speed SDIO bus,based on the signal integrity simulation in the Cadence Sigrity platform,a high-speed signal simulation method for the SDIO bus is proposed.This method has high simulation reference significance for the SDIO bus.Board-level circuit design and simulation optimization of embedded platform for Hi3516 EV200,experimental simulation of stacked structure,stacking sequence,trace length,ground via,and number of vias,optimizing PCB design,researching and analyzing S-parameters and time domain diagrams have been carried out,and a reference method of the circuit routing design of SDIO bus is proposed,and the feasibility and practical value of the scheme are demonstrated through theoretical analysis and simulation experiments,which fills the blank of SDIO bus design in the signal integrity simulation analysis.

关 键 词：SDIO总线 信号完整性 Cadence Sigrity 高速数字电路 拓扑结构 

分 类 号：TN7[电子电信—电路与系统]