一种应用于SoC的高稳定性无片外电容LDO稳压器  

A high stable output-capacitor-less LDO regulator for SoC applications

作　　者：曾范洋 蒋品群[1] 宋树祥[1] 蔡超波 刘振宇 ZENG Fanyang;JIANG Pinqun;SONG Shuxiang;CAI Chaobo;LIU Zhenyu(College of Electronic Engineering,Guangxi Normal University,Guilin 541004,Guangxi Zhuang Autonomous Region,China)

机构地区：[1]广西师范大学电子工程学院,广西桂林541004

出　　处：《电子元件与材料》2022年第3期278-283,共6页Electronic Components And Materials

基　　金：国家自然科学基金(62061005);广西高校中青年教师科研基础能力提升项目(2020KY02028);广西研究生教育创新计划项目(YCSW2021070)。

摘　　要：为了减少负载电流瞬态变化对低压差线性稳压器(LDO)输出电压稳定性的不利影响,设计了一种应用于片上系统(SoC)的高稳定性无片外电容LDO稳压器。该电路采用密勒电容倍增补偿和零点-极点跟踪补偿技术,使LDO在不同负载条件下仍具有良好的环路稳定性。同时,通过摆率增强电路来动态调节功率晶体管的栅极电压,改善了LDO的瞬态响应特性。电路采用0.11μm标准CMOS工艺设计。后端仿真结果表明,当电源电压为1.3~3.3 V,最大输出负载电流为50 mA时,LDO输出电压的稳定值为1.21 V,静态电流为35μA,最小相位裕度为64.43°。当负载电流以1μs的时间在1~50 mA之间跃变时,与未加入摆率增强电路的LDO相比,输出电压的下冲幅度减少了126 mV,下降了42.5%;过冲幅度减少了44 mV,下降了20.6%。To reduce the adverse effect of load current transient changes on the output voltage stability of the low-dropout linear regulator(LDO),a high-stable capacitor-free LDO was designed for system-on-chip(SoC)applications.Miller capacitor multiplier and zero-pole tracking compensation techniques were used to ensure that the LDO remains good loop stability under different load conditions.In addition,the gate voltage of the power transistor was dynamically adjusted through the slew-rate enhancement circuit,which improved the transient response characteristics of the LDO.The circuit was designed using the 0.11μm standard CMOS process.The post-simulation results show that the output voltage is 1.21 V with quiescent current of 35μA when the supply voltage is from 1.3 V to 3.3 V and the maximum output load current is 50 mA.The minimum phase margin is 64.43°.Compared with the LDO without the slew-rate enhancement circuit,when the load current steps from 1 mA to 50 mA within 1μs,the undershoot(overshoot)of the output voltage was reduced by 126 mV(44 mV),which is reduced by 42.5%(20.6%).

关 键 词：低压差线性稳压器 无片外电容 高稳定性 频率补偿 摆率增强 

分 类 号：TN432[电子电信—微电子学与固体电子学]